rmp_cntl.lst

TI 的DSP2407A的无速度传感器永磁同步电机FOC控制程序

         001c 002b' 
     110                                    ; ARP=AR2, AR0->FR0, AR2->setpt_value
     111            ;----------------------------------------------------------------------------------
     112 001d       DEC_VALUE               ; ARP=AR2, AR0->FR0, AR2->setpt_value
     113            ;----------------------------------------------------------------------------------
     114 001d 1080          LACC    *               ; ACC = setpt_value  (Q15)
     115                                                    ; ARP=AR2, AR0->FR0, AR2->setpt_value
     116            ;----------------------------------------------------------------------------------
     117 001e ba01          SUB             #1              ; ACC = setpt_value - 1  (Q15)
     118                                                    ; ARP=AR2, AR0->FR0, AR2->setpt_value
     119            ;----------------------------------------------------------------------------------
     120 001f 9080          SACL    *               ; setpt_value = setpt_value - 1  (Q15)
     121                                                    ; ARP=AR2, AR0->FR0, AR2->setpt_value
     122            ;----------------------------------------------------------------------------------
     123 0020 7c03                  SBRK    #3              ; ARP=AR2, AR0->FR0, AR2->rmp_lo_limit 
     124            ;----------------------------------------------------------------------------------
     125 0021 3080                  SUB             *               ; ACC = setpt_value - 1 - rmp_lo_limit (Q15)
     126                                                            ; ARP=AR2, AR0->FR0, AR2->rmp_lo_limit
     127            ;----------------------------------------------------------------------------------
     128 0022 7803                  ADRK    #3              ; ARP=AR2, AR0->FR0, AR2->setpt_value
     129            ;----------------------------------------------------------------------------------
     130 0023 e38c          BCND    SRC_1, GEQ ; Branch to SRC_1 if ACC >= 0
         0024 0037' 
     131                                    ; ARP=AR2, AR0->FR0, AR2->setpt_value   
     132            ;----------------------------------------------------------------------------------
     133 0025 7c03          SBRK    #3              ; ARP=AR2, AR0->FR0, AR2->rmp_lo_limit
     134            ;----------------------------------------------------------------------------------
     135 0026 1080          LACC    *               ; ACC = rmp_lo_limit  (Q15)
     136                                                    ; ARP=AR2, AR0->FR0, AR2->rmp_lo_limit
     137            ;----------------------------------------------------------------------------------
     138 0027 7803          ADRK    #3              ; ARP=AR2, AR0->FR0, AR2->setpt_value           
     139            ;----------------------------------------------------------------------------------
     140 0028 9080                  SACL    *               ; setpt_value = rmp_lo_limit  (Q15)
     141                                                            ; ARP=AR2, AR0->FR0, AR2->setpt_value 
     142            ;----------------------------------------------------------------------------------
     143 0029 7980          B               SRC_1   ; Branch to SRC_1
         002a 0037' 
     144                                                    ; ARP=AR2, AR0->FR0, AR2->setpt_value
     145            ;----------------------------------------------------------------------------------
     146 002b       INC_VALUE               ; ARP=AR2, AR0->FR0, AR2->setpt_value
     147            ;----------------------------------------------------------------------------------
     148 002b 1080                  LACC    *               ; ACC = setpt_value  (Q15)
     149                                                            ; ARP=AR2, AR0->FR0, AR2->setpt_value
     150            ;----------------------------------------------------------------------------------
     151 002c b801          ADD             #1              ; ACC = set_value + 1  (Q15)
     152                                                    ; ARP=AR2, AR0->FR0, AR2->setpt_value
     153            ;----------------------------------------------------------------------------------
     154 002d 9080          SACL    *               ; setpt_value = set_value + 1  (Q15)
     155                                                    ; ARP=AR2, AR0->FR0, AR2->setpt_value
     156            ;----------------------------------------------------------------------------------
     157 002e 7c02          SBRK    #2              ; ARP=AR2, AR0->FR0, AR2->rmp_hi_limit
TMS320C24xx COFF Assembler Version 7.04  Fri May 04 19:50:41 2007
Copyright (c) 1987-2003  Texas Instruments Incorporated 
rmp_cntl.asm                                                         PAGE    4

     158            ;----------------------------------------------------------------------------------
     159 002f 3080                  SUB             *               ; ACC = set_value + 1 - rmp_hi_limit (Q15)
     160                                                            ; ARP=AR2, AR0->FR0, AR2->rmp_hi_limit
     161            ;----------------------------------------------------------------------------------
     162 0030 7802                  ADRK    #2              ; ARP=AR2, AR0->FR0, AR2->setpt_value
     163            ;----------------------------------------------------------------------------------
     164 0031 e3cc                  BCND    SRC_1, LEQ ; Branch to SRC_1 if ACC <= 0
         0032 0037' 
     165                                                            ; ARP=AR2, AR0->FR0, AR2->setpt_value
     166            ;----------------------------------------------------------------------------------
     167 0033 7c02                  SBRK    #2              ; ARP=AR2, AR0->FR0, AR2->rmp_hi_limit
     168            ;----------------------------------------------------------------------------------
     169 0034 1080          LACC    *               ; ACC = rmp_hi_limit  (Q15)
     170                                                    ; ARP=AR2, AR0->FR0, AR2->rmp_hi_limit
     171            ;----------------------------------------------------------------------------------
     172 0035 7802                  ADRK    #2              ; ARP=AR2, AR0->FR0, AR2->setpt_value
     173            ;----------------------------------------------------------------------------------
     174 0036 9080                  SACL    *               ; setpt_value = rmp_hi_limit (Q15)
     175                                                            ; ARP=AR2, AR0->FR0, AR2->setpt_value
     176            ;----------------------------------------------------------------------------------
     177 0037       SRC_1                   ; ARP=AR2, AR0->FR0, AR2->setpt_value
     178            ;----------------------------------------------------------------------------------
     179 0037 7c01                  SBRK    #1              ; ARP=AR2, AR0->FR0, AR2->rmp_delay_cntl
     180            ;----------------------------------------------------------------------------------
     181 0038 ae80          SPLK    #0,*    ; rmp_delay_cntl = 0
         0039 0000  
     182                                    ; ARP=AR2, AR0->FR0, AR2->rmp_delay_cntl
     183            ;----------------------------------------------------------------------------------
     184 003a 7c04                  SBRK    #4              ; ARP=AR2, AR0->FR0, AR2->target_value
     185            ;----------------------------------------------------------------------------------
     186 003b       SRC_EXIT                ; ARP=AR2, AR0->FR0, AR2->target_value
     187            ;----------------------------------------------------------------------------------
     188 003b 7980                  B               RMPCNTL_END ; Branch to RMPCNTL_END     
         003c 0041' 
     189                                                            ; ARP=AR2, AR0->FR0, AR2->target_value
     190            ;----------------------------------------------------------------------------------
     191 003d 7804          ADRK    #4              ; ARP=AR2, AR0->FR0, AR2->rmp_delay_cntl 
     192            ;----------------------------------------------------------------------------------
     193 003e       SET_FLG                                 ; ARP=AR2, AR0->FR0, AR2->rmp_delay_cntl
     194            ;----------------------------------------------------------------------------------
     195 003e 7802                  ADRK    #2              ; ARP=AR2, AR0->FR0, AR2->s_eq_t_flg
     196            ;----------------------------------------------------------------------------------
     197 003f ae80          SPLK    #7FFFh,* ; s_eq_t_flg = 7FFFh
         0040 7fff  
     198                                                    ; ARP=AR2, AR0->FR0, AR2->s_eq_t_flg
     199            ;----------------------------------------------------------------------------------
     200 0041       RMPCNTL_END
     201            ;----------------------------------------------------------------------------------
     202 0041       _rmp_cntl_calc_exit:
     203 0041 8b89          MAR     *,AR1   ; can be removed if this condition is met on
     204                                    ; every path to this code. (i.e., ARP=AR1 here)
     205            
     206 0042 be42          CLRC    OVM
     207 0043 be46          CLRC    SXM
TMS320C24xx COFF Assembler Version 7.04  Fri May 04 19:50:41 2007
Copyright (c) 1987-2003  Texas Instruments Incorporated 
rmp_cntl.asm                                                         PAGE    5

     208            
     209 0044 7c01          SBRK    #(__rmp_cntl_calc_framesize +1)
     210 0045 0090          LAR     AR0,*-
     211 0046 7680          PSHD    *
     212                    
     213 0047 ef00          RET
     214            
     215            
     216            

 No Errors,  No Warnings