📄 pid_reg3.lst
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150 ; ARP=AR2, AR0->FR0, AR2->pid_out_reg3
151 ;----------------------------------------------------------------------------------
152 0028 7980 B UPDATE_REG3 ; ARP=AR2, AR0->FR0, AR2->pid_out_reg3
0029 0033'
153 ;----------------------------------------------------------------------------------
154 002a SAT_MAX_REG3 ; ARP=AR2, AR0->FR0, AR2->uprsat_reg3
155 ;----------------------------------------------------------------------------------
156 002a 7801 ADRK #1 ; ARP=AR2, AR0->FR0, AR2->pid_out_max
157 ;----------------------------------------------------------------------------------
158 002b 1080 LACC * ; ACC = pid_out_max (Q15)
159 ; ARP=AR2, AR0->FR0, AR2->pid_out_max
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:38 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
pid_reg3.asm PAGE 4
160 ;----------------------------------------------------------------------------------
161 002c 7802 ADRK #2 ; ARP=AR2, AR0->FR0, AR2->pid_out_reg3
162 ;----------------------------------------------------------------------------------
163 002d 9080 SACL * ; pid_out_reg3 = pid_out_max (Q15)
164 ; ARP=AR2, AR0->FR0, AR2->pid_out_reg3
165 ;----------------------------------------------------------------------------------
166 002e 7980 B UPDATE_REG3 ; ARP=AR2, AR0->FR0, AR2->pid_out_reg3
002f 0033'
167 ;----------------------------------------------------------------------------------
168 0030 SAT_MIN_REG3 ; ARP=AR2, AR0->FR0, AR2->uprsat_reg3
169 ;----------------------------------------------------------------------------------
170 0030 7802 ADRK #2 ; ARP=AR2, AR0->FR0, AR2->pid_out_min
171 ;----------------------------------------------------------------------------------
172 0031 10a0 LACC *+ ; ACC = pid_out_min (Q15)
173 ; ARP=AR2, AR0->FR0, AR2->pid_out_reg3
174 ;----------------------------------------------------------------------------------
175 0032 9080 SACL * ; pid_out_reg3 = pid_out_min (Q15)
176 ; ARP=AR2, AR0->FR0, AR2->pid_out_reg3
177 ;----------------------------------------------------------------------------------
178 0033 UPDATE_REG3 ; ARP=AR2, AR0->FR0, AR2->pid_out_reg3
179 ;----------------------------------------------------------------------------------
180 0033 1f80 LACC *,15 ; ACC = pid_out_reg3 (Q30)
181 ; ARP=AR2, AR0->FR0, AR2->pid_out_reg3
182 ;----------------------------------------------------------------------------------
183 0034 7c03 SBRK #3 ; ARP=AR2, AR0->FR0, AR2->uprsat_reg3
184 ;----------------------------------------------------------------------------------
185 0035 6580 SUB *,16 ; ACC = pid_out_reg3 - uprsat_reg3 (Q30)
186 ; ARP=AR2, AR0->FR0, AR2->uprsat_reg3
187 ;----------------------------------------------------------------------------------
188 0036 7804 ADRK #4 ; ARP=AR2, AR0->FR0, AR2->saterr_reg3
189 ;----------------------------------------------------------------------------------
190 0037 98a0 SACH *+ ; saterr_reg3 = pid_out_reg3 - uprsat_reg3 (Q14)
191 ; ARP=AR2, AR0->FR0, AR2->Ki_reg3
192 ;----------------------------------------------------------------------------------
193 0038 bf03 SPM 3 ; Set right shifted 6 bit
194 ; ARP=AR2, AR0->FR0, AR2->Ki_reg3
195 ;----------------------------------------------------------------------------------
196 0039 7380 LT * ; TREG = Ki (Q31-16 bit)
197 ; ARP=AR2, AR0->FR0, AR2->Ki_reg3
198 ;----------------------------------------------------------------------------------
199 003a 7c0a SBRK #10 ; ARP=AR2, AR0->FR0, AR2->up_reg3
200 ;----------------------------------------------------------------------------------
201 003b 5480 MPY * ; PREG = Ki*up (Q38)
202 ; ARP=AR2, AR0->FR0, AR2->up_reg3
203 ;----------------------------------------------------------------------------------
204 003c be03 PAC ; ACC = Ki*up (Q32)
205 ; ARP=AR2, AR0->FR0, AR2->up_reg3
206 ;----------------------------------------------------------------------------------
207 003d be0a SFR ; ACC = Ki*up (Q31)
208 ; ARP=AR2, AR0->FR0, AR2->up_reg3
209 ;----------------------------------------------------------------------------------
210 003e be0a SFR ; ACC = Ki*up (Q30)
211 ; ARP=AR2, AR0->FR0, AR2->up_reg3
212 ;----------------------------------------------------------------------------------
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:38 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
pid_reg3.asm PAGE 5
213 003f bf01 SPM 1 ; Set left shifted 1 bit
214 ; ARP=AR2, AR0->FR0, AR2->up_reg3
215 ;----------------------------------------------------------------------------------
216 0040 780b ADRK #11 ; ARP=AR2, AR0->FR0, AR2->Kc_reg3
217 ;----------------------------------------------------------------------------------
218 0041 7380 LT * ; TREG = Kc (Q15)
219 ; ARP=AR2, AR0->FR0, AR2->Kc_reg3
220 ;----------------------------------------------------------------------------------
221 0042 7c02 SBRK #2 ; ARP=AR2, AR0->FR0, AR2->saterr_reg3
222 ;----------------------------------------------------------------------------------
223 0043 5480 MPY * ; PREG = Kc*saterr_reg3 (Q29)
224 ; ARP=AR2, AR0->FR0, AR2->saterr_reg3
225 ;----------------------------------------------------------------------------------
226 0044 be04 APAC ; ACC = Ki*up + Kc*(pid_out_reg3-uprsat_reg3) (Q30)
227 ; ARP=AR2, AR0->FR0, AR2->saterr_reg3
228 ;----------------------------------------------------------------------------------
229 0045 7c07 SBRK #7 ; ARP=AR2, AR0->FR0, AR2->ui_lo_reg3
230 ;----------------------------------------------------------------------------------
231 0046 6290 ADDS *- ; ACC = ui + Ki*up + Kc*(pid_out_reg3-uprsat_reg3) (Q30)
232 ; ARP=AR2, AR0->FR0, AR2->ui_hi_reg3
233 ;----------------------------------------------------------------------------------
234 0047 61a0 ADDH *+ ; ACC = ui + Ki*up + Kc*(pid_out_reg3-uprsat_reg3) (Q30)
235 ; ARP=AR2, AR0->FR0, AR2->ui_lo_reg3
236 ;----------------------------------------------------------------------------------
237 0048 9090 SACL *- ; ui = ui + Ki*up + Kc*(pid_out_reg3-uprsat_reg3) (Q30)
238 ; ARP=AR2, AR0->FR0, AR2->ui_hi_reg3
239 ;----------------------------------------------------------------------------------
240 0049 9880 SACH * ; ui = ui + Ki*up + Kc*(pid_out_reg3-uprsat_reg3) (Q30)
241 ; ARP=AR2, AR0->FR0, AR2->ui_hi_reg3
242 ;----------------------------------------------------------------------------------
243 004a 780b ADRK #11 ; ARP=AR2, AR0->FR0, AR2->Kd_reg3
244 ;----------------------------------------------------------------------------------
245 004b 7380 LT * ; TREG = Kd (Q14)
246 ; ARP=AR2, AR0->FR0, AR2->Kd_reg3
247 ;----------------------------------------------------------------------------------
248 004c 7c0c SBRK #12 ; ARP=AR2, AR0->FR0, AR2->up_reg3
249 ;----------------------------------------------------------------------------------
250 004d 5480 MPY * ; PREG = Kd*up (Q28)
251 ; ARP=AR2, AR0->FR0, AR2->up_reg3
252 ;----------------------------------------------------------------------------------
253 004e be03 PAC ; ACC = Kd*up (Q29)
254 ; ARP=AR2, AR0->FR0, AR2->up_reg3
255 ;----------------------------------------------------------------------------------
256 004f 780d ADRK #13 ; ARP=AR2, AR0->FR0, AR2->up1_reg3
257 ;----------------------------------------------------------------------------------
258 0050 5480 MPY * ; PREG = Kd*up1 (Q28)
259 ; ARP=AR2, AR0->FR0, AR2->up1_reg3
260 ;----------------------------------------------------------------------------------
261 0051 be05 SPAC ; ACC = Kd*up - Kd*up1 (Q29)
262 ; ARP=AR2, AR0->FR0, AR2->up1_reg3
263 ;----------------------------------------------------------------------------------
264 0052 7c0a SBRK #10 ; ARP=AR2, AR0->FR0, AR2->ud_lo_reg3
265 ;----------------------------------------------------------------------------------
266 0053 91a0 SACL *+,1 ; ud_lo_reg3 = Kd*up - Kd*up1 (Q30)
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:38 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
pid_reg3.asm PAGE 6
267 ; ARP=AR2, AR0->FR0, AR2->ud_hi_reg3
268 ;----------------------------------------------------------------------------------
269 0054 9980 SACH *,1 ; ud_hi_reg3 = Kd*up - Kd*up1 (Q30)
270 ; ARP=AR2, AR0->FR0, AR2->ud_hi_reg3
271 ;----------------------------------------------------------------------------------
272 0055 7c04 SBRK #4 ; ARP=AR2, AR0->FR0, AR2->up_reg3
273 ;----------------------------------------------------------------------------------
274 0056 1080 LACC * ; ACC = up_reg3 (Q14)
275 ; ARP=AR2, AR0->FR0, AR2->up_reg3
276 ;----------------------------------------------------------------------------------
277 0057 780d ADRK #13 ; ARP=AR2, AR0->FR0, AR2->up1_reg3
278 ;----------------------------------------------------------------------------------
279 0058 9089 SACL *,AR1 ; up1_reg3 = up_reg3 (Q14)
280 ; ARP=AR2, AR0->FR0, AR2->up1_reg3, ARP=AR1
281 ;----------------------------------------------------------------------------------
282 0059 _pid_reg3_calc_exit:
283 ;; MAR *,AR1 ; can be removed if this condition is met on
284 ; every path to this code. (i.e., ARP=AR1 here)
285
286 0059 bf00 SPM 0
287 005a be42 CLRC OVM
288 005b be46 CLRC SXM
289
290 005c 7c01 SBRK #(__pid_reg3_calc_framesize+1)
291 005d 0090 LAR AR0,*-
292 005e 7680 PSHD *
293
294 005f ef00 RET
295
296
297
No Errors, No Warnings
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