📄 pid_reg3.lst
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dspa -l -s -i../include -v2xx -iD:/CCStudio_v3.1/c2400/cgtools/include -g pid_reg3.asm ../obj\pid_reg3.obj
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:38 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
pid_reg3.asm PAGE 1
1 ;=====================================================================================
2 ; File name: PID_REG3.ASM
3 ;
4 ; Originator: Digital Control Systems Group
5 ; Texas Instruments
6 ;
7 ; Description: Digital PID controller with anti-windup correction
8 ;
9 ;=====================================================================================
10 ; History:
11 ;-------------------------------------------------------------------------------------
12 ; 02-08-2001 Release Rev 1.00
13 ;================================================================================
14 ; Applicability: F240,F241,C242,F243,F24xx. (Peripheral Independent).
15 ;================================================================================
16 ; Routine Name: pid_reg3_calc Type: C Call
17 ;
18 ; C prototype : void pid_reg3_calc(struct PIDREG3 *p);
19 ;
20 ; The struct object is defined in the header file "pid_reg3.h" as follows:
21 ;
22 ; typedef struct { int pid_ref_reg3; /* Input: Reference input (Q15) */
23 ; int pid_fdb_reg3; /* Input: Feedback input (Q15) */
24 ; int e_reg3; /* Variable: Error (Q14) */
25 ; int Kp_reg3; /* Parameter: Proportional gain (Q15) */
26 ; int up_reg3; /* Variable: Proportional output (Q14) */
27 ; int ui_hi_reg3; /* Variable: Integral output (Q30) */
28 ; int ui_lo_reg3; /* Variable: Integral output (Q30) */
29 ; int ud_lo_reg3; /* Variable: Derivative output (Q30) */
30 ; int ud_hi_reg3; /* Variable: Derivative output (Q30) */
31 ; int uprsat_reg3; /* Variable: Pre-saturated output (Q14) */
32 ; int pid_out_max; /* Parameter: Maximum output (Q15) */
33 ; int pid_out_min; /* Parameter: Minimum output (Q15) */
34 ; int pid_out_reg3; /* Output: PID output (Q15) */
35 ; int saterr_reg3; /* Variable: Saturated difference (Q14) */
36 ; int Ki_reg3; /* Parameter: Integral gain (Q31-16bit) */
37 ; int Kc_reg3; /* Parameter: Integral correction gain (Q15) */
38 ; int Kd_reg3; /* Parameter: Derivative gain (Q14) */
39 ; int up1_reg3; /* Variable: Previous proportional output (Q14)
40 ; int (*calc)(); /* Pointer to calculation function */
41 ; } PIDREG3;
42 ;
43 ; Frame Usage Details:
44 ; step | a | b | c | d
45 ;____________|_____________|______________|______________|_____________
46 ; AR0 | | | |
47 ;
48 ;================================================================================
49 .def _pid_reg3_calc
50 ;================================================================================
51 0000 __pid_reg3_calc_framesize .set 0000h
52 ;================================================================================
53 0000 _pid_reg3_calc:
54 ; Assume
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:38 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
pid_reg3.asm PAGE 2
55 0000 8aa0 POPD *+ ; Keep return address
56 0001 80a0 SAR AR0,*+ ; Keep old frame pointer (FP)
57 0002 8180 SAR AR1,* ; Keep old stack pointer (SP)
58 0003 b000 LARK AR0,__pid_reg3_calc_framesize ; Load AR0 with frame size
59 0004 00e8 LAR AR0,*0+,AR0 ; AR0->FP0 (new FP), ARP=AR0
60
61 ;================================================================================
62 0005 7c03 SBRK #3 ; ARP=AR0, AR0->FR0-3 (1st argument)
63 ;----------------------------------------------------------------------------------
64 0006 0280 LAR AR2,* ; ARP=AR0, AR0->pid_ref_reg3, AR2->pid_ref_reg3
65 ;----------------------------------------------------------------------------------
66 0007 7803 ADRK #3 ; ARP=AR0, AR0->FR0, AR2->pid_ref_reg3
67 ;----------------------------------------------------------------------------------
68 0008 8b8a MAR *,AR2 ; ARP=AR2, AR0->FR0, AR2->pid_ref_reg3
69 ;----------------------------------------------------------------------------------
70 0009 be47 SETC SXM ; Turn sign extension mode on
71 ; ARP=AR2, AR0->FR0, AR2->pid_ref_reg3
72 ;----------------------------------------------------------------------------------
73 000a be43 SETC OVM ; Set overflow mode
74 ; ARP=AR2, AR0->FR0, AR2->pid_ref_reg3
75 ;----------------------------------------------------------------------------------
76 000b bf00 SPM 0 ; Reset product mode
77 ; ARP=AR2, AR0->FR0, AR2->pid_ref_reg3
78 ;----------------------------------------------------------------------------------
79 000c 1fa0 LACC *+,15 ; ACC = pid_ref_reg3 (Q30)
80 ; ARP=AR2, AR0->FR0, AR2->pid_fdb_reg3
81 ;----------------------------------------------------------------------------------
82 000d 3fa0 SUB *+,15 ; ACC = pid_ref_reg3 - pid_fdb_reg3 (Q30)
83 ; ARP=AR2, AR0->FR0, AR2->e_reg3
84 ;----------------------------------------------------------------------------------
85 000e 9880 SACH * ; e_reg3 = pid_ref_reg3 - pid_fdb_reg3 (Q14)
86 ; ARP=AR2, AR0->FR0, AR2->e_reg3
87 ;----------------------------------------------------------------------------------
88 000f 73a0 LT *+ ; TREG = e_reg3 (Q14)
89 ; ARP=AR2, AR0->FR0, AR2->Kp_reg3
90 ;----------------------------------------------------------------------------------
91 0010 54a0 MPY *+ ; PREG = Kp_reg3*e_reg3 (Q29)
92 ; ARP=AR2, AR0->FR0, AR2->up_reg3
93 ;----------------------------------------------------------------------------------
94 0011 be03 PAC ; ACC = Kp_reg3*e_reg3 (Q29)
95 ; ARP=AR2, AR0->FR0, AR2->up_reg3
96 ;----------------------------------------------------------------------------------
97 0012 99a0 SACH *+,1 ; up_reg3 = Kp_reg3*e_reg3 (Q14)
98 ; ARP=AR2, AR0->FR0, AR2->ui_hi_reg3
99 ;----------------------------------------------------------------------------------
100 0013 6aa0 LACC *+,16 ; ACC = ui (Q30)
101 ; ARP=AR2, AR0->FR0, AR2->ui_lo_reg3
102 ;----------------------------------------------------------------------------------
103 0014 62a0 ADDS *+ ; ACC = ui (Q30)
104 ; ARP=AR2, AR0->FR0, AR2->ud_lo_reg3
105 ;----------------------------------------------------------------------------------
106 0015 62a0 ADDS *+ ; ACC = ui + ud (Q30)
107 ; ARP=AR2, AR0->FR0, AR2->ud_hi_reg3
108 ;----------------------------------------------------------------------------------
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:38 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
pid_reg3.asm PAGE 3
109 0016 6180 ADDH * ; ACC = ui + ud (Q30)
110 ; ARP=AR2, AR0->FR0, AR2->ud_hi_reg3
111 ;----------------------------------------------------------------------------------
112 0017 7c04 SBRK #4 ; ARP=AR2, AR0->FR0, AR2->up_reg3
113 ;----------------------------------------------------------------------------------
114 0018 6180 ADDH * ; ACC = up + ui + ud (Q30)
115 ; ARP=AR2, AR0->FR0, AR2->up_reg3
116 ;----------------------------------------------------------------------------------
117 0019 7805 ADRK #5 ; ARP=AR2, AR0->FR0, AR2->uprsat_reg3
118 ;----------------------------------------------------------------------------------
119 001a 9880 SACH * ; uprsat_reg3 = up + ui + ud (Q14)
120 ; ARP=AR2, AR0->FR0, AR2->uprsat_reg3
121 ;----------------------------------------------------------------------------------
122 001b 6aa0 LACC *+,16 ; ACC = uprsat_reg3 (Q14)
123 ; ARP=AR2, AR0->FR0, AR2->pid_out_max
124 ;----------------------------------------------------------------------------------
125 001c 3f90 SUB *-,15 ; ACC = uprsat_reg3 - pid_out_max (Q14)
126 ; ARP=AR2, AR0->FR0, AR2->uprsat_reg3
127 ;----------------------------------------------------------------------------------
128 001d e304 BCND SAT_MAX_REG3,GT ; Branch to SAT_MAX_REG3 if uprsat_reg3 > pid_out_max
001e 002a'
129 ; ARP=AR2, AR0->FR0, AR2->uprsat_reg3
130 ;----------------------------------------------------------------------------------
131 001f 6a80 LACC *,16 ; ACC = uprsat_reg3 (Q14)
132 ; ARP=AR2, AR0->FR0, AR2->uprsat_reg3
133 ;----------------------------------------------------------------------------------
134 0020 7802 ADRK #2 ; ARP=AR2, AR0->FR0, AR2->pid_out_min
135 ;----------------------------------------------------------------------------------
136 0021 3f80 SUB *,15 ; ACC = uprsat_reg3 - pid_out_min (Q14)
137 ; ARP=AR2, AR0->FR0, AR2->pid_out_min
138 ;----------------------------------------------------------------------------------
139 0022 7c02 SBRK #2 ; ARP=AR2, AR0->FR0, AR2->uprsat_reg3
140 ;----------------------------------------------------------------------------------
141 0023 e344 BCND SAT_MIN_REG3,LT ; Branch to SAT_MIN_REG3 if uprsat_reg3 < pid_out_min
0024 0030'
142 ; ARP=AR2, AR0->FR0, AR2->uprsat_reg3
143 ;----------------------------------------------------------------------------------
144 0025 6a80 LACC *,16 ; ACC = uprsat_reg3 (Q30)
145 ; ARP=AR2, AR0->FR0, AR2->uprsat_reg3
146 ;----------------------------------------------------------------------------------
147 0026 7803 ADRK #3 ; ARP=AR2, AR0->FR0, AR2->pid_out_reg3
148 ;----------------------------------------------------------------------------------
149 0027 9980 SACH *,1 ; pid_out_reg3 = uprsat_reg3 (Q15)
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