📄 svgen_dq.lst
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473 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
474 ;--------------------------------------------------------------------------------
475 00a6 309a SUB *-,AR2 ; ACC = 1-t1=t2.
476 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
477 ;--------------------------------------------------------------------------------
478 00a7 be0a SFR ; ACC = (1-t1=t2)/2.
479 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
480 ;--------------------------------------------------------------------------------
481
482 00a8 8ba0 MAR *+ ; AR2++. Now AR2 -> tb
483 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR3.
484 ;--------------------------------------------------------------------------------
485 00a9 90ab SACL *+,AR3 ; Store tb
486 ; ARP=AR3. AR0->FR1 AR2->tc AR3->FR3.
487 ;--------------------------------------------------------------------------------
488 00aa 20aa ADD *+,AR2 ; ACC = tb + t1.
489 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
490 ;--------------------------------------------------------------------------------
491 00ab 908b SACL *,AR3 ; Store tc = tb + t1.
492 ; ARP=AR3. AR0->FR1 AR2->tc AR3->FR4.
493 ;--------------------------------------------------------------------------------
494 00ac 208a ADD *,AR2 ; ACC = tc + t2.
495 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
496 ;--------------------------------------------------------------------------------
497 00ad 7c02 SBRK #2 ; Point AR2 to ta.
498 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
499 ;--------------------------------------------------------------------------------
500 00ae 90a0 SACL *+ ; Store ta.
501 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
502 ;--------------------------------------------------------------------------------
503 00af 7980 B SV_POST_PROCESS
00b0 00c6'
504 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
505 ;--------------------------------------------------------------------------------
506 ; Sector Subroutine #6. On arrival :
507 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
508 ;--------------------------------------------------------------------------------
509 00b1 7c01 SECTOR_SR6: SBRK #1 ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR3.
510
511 00b2 10ab LACC *+,AR3 ; ACC = Y
512 ; ARP=AR3. AR0->FR2 AR2->ta AR3->FR3.
513 ;--------------------------------------------------------------------------------
514 00b3 be02 NEG ; ARP=AR3. AR0->FR2 AR2->ta AR3->FR3.
515 ;--------------------------------------------------------------------------------
516 00b4 90a8 SACL *+,AR0 ; Store t1 = -Y. ( FR3 = t1.)
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:44 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
svgen_dq.asm PAGE 11
517 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR4.
518 ;--------------------------------------------------------------------------------
519 00b5 109b LACC *-,AR3 ; ACC = Z.
520 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
521 ;--------------------------------------------------------------------------------
522 00b6 be02 NEG ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
523 ;--------------------------------------------------------------------------------
524 00b7 9090 SACL *- ; Store t2 = -Z. ( FR4 = t2.)
525 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
526 ;--------------------------------------------------------------------------------
527 00b8 bf80 LACC #7fffh ; ACCL= 1 (Q15).
00b9 7fff
528 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
529 ;--------------------------------------------------------------------------------
530 00ba 30a0 SUB *+ ; ACC = 1-t1.
531 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
532 ;--------------------------------------------------------------------------------
533 00bb 309a SUB *-,AR2 ; ACC = 1-t1=t2.
534 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
535 ;--------------------------------------------------------------------------------
536 00bc be0a SFR ; ACC = (1-t1=t2)/2.
537 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
538 ;--------------------------------------------------------------------------------
539 00bd 7802 ADRK #2 ; AR2+=2. Now AR2 -> tc
540 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR3.
541 ;--------------------------------------------------------------------------------
542 00be 908b SACL *,AR3 ; Store tc
543 ; ARP=AR3. AR0->FR1 AR2->tc AR3->FR3.
544 ;--------------------------------------------------------------------------------
545 00bf 20aa ADD *+,AR2 ; ACC = tc + t1.
546 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
547 ;--------------------------------------------------------------------------------
548 00c0 7c02 SBRK #2 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
549 ;--------------------------------------------------------------------------------
550 00c1 90ab SACL *+,AR3 ; Store ta = tc + t1.
551 ; ARP=AR3. AR0->FR1 AR2->tb AR3->FR4.
552 ;--------------------------------------------------------------------------------
553 00c2 208a ADD *,AR2 ; ACC = ta + t2.
554 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
555 ;--------------------------------------------------------------------------------
556 00c3 9080 SACL * ; Store tb.
557 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
558 ;--------------------------------------------------------------------------------
559 00c4 7980 B SV_POST_PROCESS
00c5 00c6'
560 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
561 ;--------------------------------------------------------------------------------
562
563
564 00c6 SV_POST_PROCESS: ; On arrival: ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
565
566 ; Multiply tb by 2 and subtract offset = 1/2. for ta,tb,tc.
567 ;-------------------------------------------------------------------------------
568 00c6 8b90 MAR *- ; AR2--
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:44 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
svgen_dq.asm PAGE 12
569 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
570 ;-------------------------------------------------------------------------------
571 00c7 1080 LACC * ; Get ta
572 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
573 ;-------------------------------------------------------------------------------
574 00c8 bfa0 SUB #3FFFh ; Subtract offset.
00c9 3fff
575 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
576 ;-------------------------------------------------------------------------------
577 00ca 91a0 SACL *+,1 ; Store (ta-0.5)*2
578 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
579 ;-------------------------------------------------------------------------------
580 00cb 1080 LACC * ; Get tb
581 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
582 ;-------------------------------------------------------------------------------
583 00cc bfa0 SUB #3FFFh ; Subtract offset.
00cd 3fff
584 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
585 ;-------------------------------------------------------------------------------
586 00ce 91a0 SACL *+,1 ; Store (tb-0.5)*2
587 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
588 ;-------------------------------------------------------------------------------
589 00cf 1080 LACC * ; Get tc
590 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
591 ;-------------------------------------------------------------------------------
592 00d0 bfa0 SUB #3FFFh ; Subtract offset.
00d1 3fff
593 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
594 ;-------------------------------------------------------------------------------
595 00d2 9180 SACL *,1 ; Store (tc-0.5)*2
596 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
597 ;-------------------------------------------------------------------------------
598 00d3 DUMMY
599 ;-------------------------------------------------------------------------------
600 00d3 __svgendq_exit:
601 00d3 8b89 MAR *,AR1 ; can be removed if this condition is met on
602 ; every path to this code.
603
604
605 00d4 bf00 SPM 0
606 00d5 be42 CLRC OVM
607
608
609 00d6 7c06 SBRK #(__svgendq_framesize+1)
610 00d7 0090 LAR AR0,*-
611 00d8 7680 PSHD *
612 00d9 ef00 RET
613
614 ;-------------------------------------------------------------------------------
615 ;SVPWM Sector routine jump table (Used to ref with BACC instruction
616 ;-------------------------------------------------------------------------------
617 00da SECTOR_TABLE_BASE:
618
619 00da 0048' SR0 .word SECTOR_SR0
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:44 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
svgen_dq.asm PAGE 13
620 00db 0052' SR1 .word SECTOR_SR1
621 00dc 0064' SR2 .word SECTOR_SR2
622 00dd 0077' SR3 .word SECTOR_SR3
623 00de 0089' SR4 .word SECTOR_SR4
624 00df 009d' SR5 .word SECTOR_SR5
625 00e0 00b1' SR6 .word SECTOR_SR6
626 00e1 00d3' SR7 .word DUMMY
627
628
No Errors, No Warnings
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