📄 svgen_dq.lst
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313 ;--------------------------------------------------------------------------------
314 006a bf80 LACC #7fffh ; ACCL= 1 (Q15).
006b 7fff
315 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
316 ;--------------------------------------------------------------------------------
317 006c 30a0 SUB *+ ; ACC = 1-t1.
318 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
319 ;--------------------------------------------------------------------------------
320 006d 309a SUB *-,AR2 ; ACC = 1-t1-t2.
321 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
322 ;--------------------------------------------------------------------------------
323 006e be0a SFR ; ACC = (1-t1-t2)/2.
324 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
325 ;--------------------------------------------------------------------------------
326 006f 908b SACL *,AR3 ; Store ta
327 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
328 ;--------------------------------------------------------------------------------
329 0070 20aa ADD *+,AR2 ; ACC = ta + t1.
330 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
331 ;--------------------------------------------------------------------------------
332 0071 7802 ADRK #2 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
333 ;--------------------------------------------------------------------------------
334 0072 909b SACL *-,AR3 ; Store tc = ta + t1.
335 ; ARP=AR3. AR0->FR1 AR2->tb AR3->FR4.
336 ;--------------------------------------------------------------------------------
337 0073 208a ADD *,AR2 ; ACC = tc + t2.
338 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
339 ;--------------------------------------------------------------------------------
340 0074 9080 SACL * ; Store tb.
341 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
342 ;--------------------------------------------------------------------------------
343 0075 7980 B SV_POST_PROCESS
0076 00c6'
344 ;--------------------------------------------------------------------------------
345 ; Sector Subroutine #3. On arrival :
346 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
347 ;--------------------------------------------------------------------------------
348 0077 109b SECTOR_SR3: LACC *-,AR3 ; ACC = Z
349 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
350 ;--------------------------------------------------------------------------------
351 0078 be02 NEG ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
352 ;--------------------------------------------------------------------------------
353 0079 90a8 SACL *+,AR0 ; Store t1 = -Z. ( FR3 = t1.)
354 ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR4.
355 ;--------------------------------------------------------------------------------
356 007a 8b90 MAR *- ; ARP=AR0. AR0->FR0 AR2->ta AR3->FR4.
357 ;--------------------------------------------------------------------------------
358
359 007b 10ab LACC *+,AR3 ; ACC = X.
360 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:44 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
svgen_dq.asm PAGE 8
361 ;--------------------------------------------------------------------------------
362 007c 9090 SACL *- ; Store t2 = X. ( FR4 = t2.)
363 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
364 ;--------------------------------------------------------------------------------
365 007d bf80 LACC #7fffh ; ACCL= 1 (Q15).
007e 7fff
366 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
367 ;--------------------------------------------------------------------------------
368 007f 30a0 SUB *+ ; ACC = 1-t1.
369 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
370 ;--------------------------------------------------------------------------------
371 0080 309a SUB *-,AR2 ; ACC = 1-t1=t2.
372 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
373 ;--------------------------------------------------------------------------------
374 0081 be0a SFR ; ACC = (1-t1=t2)/2.
375 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
376 ;--------------------------------------------------------------------------------
377 0082 90ab SACL *+,AR3 ; Store ta
378 ; ARP=AR3. AR0->FR1 AR2->tb AR3->FR3.
379 ;--------------------------------------------------------------------------------
380 0083 20aa ADD *+,AR2 ; ACC = ta + t1
381 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
382 ;--------------------------------------------------------------------------------
383 0084 90ab SACL *+,AR3 ; Store tb = ta + t1.
384 ; ARP=AR3. AR0->FR1 AR2->tc AR3->FR4.
385 ;--------------------------------------------------------------------------------
386 0085 208a ADD *,AR2 ; ACC = tb + t2.
387 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
388 ;--------------------------------------------------------------------------------
389 0086 9090 SACL *- ; Store tc.
390 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
391 ;--------------------------------------------------------------------------------
392 0087 7980 B SV_POST_PROCESS
0088 00c6'
393 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
394 ;--------------------------------------------------------------------------------
395
396 ;--------------------------------------------------------------------------------
397 ; Sector Subroutine #4. On arrival :
398 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
399 ;--------------------------------------------------------------------------------
400 0089 7c02 SECTOR_SR4: SBRK #2 ; ARP=AR0. AR0->FR0 AR2->ta AR3->FR3.
401 ;--------------------------------------------------------------------------------
402 008a 10ab LACC *+,AR3 ; ACC = X
403 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
404 ;--------------------------------------------------------------------------------
405 008b be02 NEG ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
406 ;--------------------------------------------------------------------------------
407 008c 90a8 SACL *+,AR0 ; Store t1 = -X. ( FR3 = t1.)
408 ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR4.
409 ;--------------------------------------------------------------------------------
410 008d 8ba0 MAR *+ ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR4.
411 ;--------------------------------------------------------------------------------
412 008e 109b LACC *-,AR3 ; ACC = Z.
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:44 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
svgen_dq.asm PAGE 9
413 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
414 ;--------------------------------------------------------------------------------
415 008f 9090 SACL *- ; Store t2 = Y. ( FR4 = t2.)
416 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
417 ;--------------------------------------------------------------------------------
418 0090 bf80 LACC #7fffh ; ACCL= 1 (Q15).
0091 7fff
419 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
420 ;--------------------------------------------------------------------------------
421 0092 30a0 SUB *+ ; ACC = 1-t1.
422 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
423 ;--------------------------------------------------------------------------------
424 0093 309a SUB *-,AR2 ; ACC = 1-t1=t2.
425 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
426 ;--------------------------------------------------------------------------------
427 0094 be0a SFR ; ACC = (1-t1=t2)/2.
428 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
429 ;--------------------------------------------------------------------------------
430 0095 7802 ADRK #2 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR3.
431 ;--------------------------------------------------------------------------------
432 0096 909b SACL *-,AR3 ; Store tc
433 ; ARP=AR3. AR0->FR1 AR2->tb AR3->FR3.
434 ;--------------------------------------------------------------------------------
435 0097 20aa ADD *+,AR2 ; ACC = tc + t1
436 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
437 ;--------------------------------------------------------------------------------
438 0098 909b SACL *-,AR3 ; Store tb = tc + t1.
439 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
440 ;--------------------------------------------------------------------------------
441 0099 208a ADD *,AR2 ; ACC = tb + t2.
442 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
443 ;--------------------------------------------------------------------------------
444 009a 90a0 SACL *+ ; Store ta.
445 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
446 ;--------------------------------------------------------------------------------
447 009b 7980 B SV_POST_PROCESS
009c 00c6'
448 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
449 ;--------------------------------------------------------------------------------
450 ; Sector Subroutine #5. On arrival :
451 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
452 ;--------------------------------------------------------------------------------
453 009d 7c02 SECTOR_SR5: SBRK #2 ; ARP=AR0. AR0->FR0 AR2->ta AR3->FR3.
454
455 009e 10ab LACC *+,AR3 ; ACC = X
456 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
457 ;--------------------------------------------------------------------------------
458 009f 90a8 SACL *+,AR0 ; Store t1 = X. ( FR3 = t1.)
459 ; ^ ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR4.
460 ;--------------------------------------------------------------------------------
461 00a0 108b LACC *,AR3 ; ACC = Y.
462 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
463 ;--------------------------------------------------------------------------------
464 00a1 be02 NEG ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:44 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
svgen_dq.asm PAGE 10
465 ;--------------------------------------------------------------------------------
466 00a2 9090 SACL *- ; Store t2 = -Y. ( FR4 = t2.)
467 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
468 ;--------------------------------------------------------------------------------
469 00a3 bf80 LACC #7fffh ; ACCL= 1 (Q15).
00a4 7fff
470 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
471 ;--------------------------------------------------------------------------------
472 00a5 30a0 SUB *+ ; ACC = 1-t1.
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