📄 svgen_dq.lst
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157 ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
158 ;--------------------------------------------------------------------------------
159 002e e3cc BCND vref1_neg,LEQ
002f 0035'
160 ; If vb<0 then do not set bit 1 of sector.
161 ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
162 ;--------------------------------------------------------------------------------
163 0030 8b8b MAR *,AR3 ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
164 ;--------------------------------------------------------------------------------
165 0031 1080 LACC * ; Get sector code.
166 ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
167 ;--------------------------------------------------------------------------------
168 0032 bfc0 OR #1 ; Set bit 0.
0033 0001
169 ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
170 ;--------------------------------------------------------------------------------
171 0034 9088 SACL *,AR0 ; Store sector code
172 ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
173 0035 vref1_neg:
174 ;--------------------------------------------------------------------------------
175 ; X,Y,Z calculation:
176 ;--------------------------------------------------------------------------------
177 0035 8b8a MAR *,AR2 ; ARP=AR2. AR0->FR0 AR2->q AR3->FR3
178 ;--------------------------------------------------------------------------------
179 0036 1098 LACC *-,AR0 ; ACC = q.
180 ; ARP=AR0. AR0->FR0 AR2->d AR3->FR3
181 ;--------------------------------------------------------------------------------
182 0037 90a0 SACL *+ ; Store FR0=X=q.
183 ; ARP=AR0. AR0->FR1 AR2->d AR3->FR3
184 ;--------------------------------------------------------------------------------
185 0038 ae80 SPLK #28377,* ;FR1 = sqrt(3) / 2.
0039 6ed9
186 ; ARP=AR0. AR0->FR1 AR2->d AR3->FR3
187 ;--------------------------------------------------------------------------------
188 003a 738a LT *,AR2 ; TREG = sqrt(3) / 2.
189 ; ARP=AR2. AR0->FR1 AR2->d AR3->FR3
190 ;--------------------------------------------------------------------------------
191 003b 54a0 MPY *+ ; PREG = d * sqrt(3) / 2.
192 ; ARP=AR2. AR0->FR1 AR2->q AR3->FR3
193 ;--------------------------------------------------------------------------------
194 003c be03 PAC ; ACC = d * sqrt(3) / 2.
195 ; ARP=AR2. AR0->FR1 AR2->q AR3->FR3
196 ;--------------------------------------------------------------------------------
197 003d 2f88 ADD *,15,AR0 ; ACCH= q/2 + d * sqrt(3) / 2.
198 ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
199 ;--------------------------------------------------------------------------------
200 003e 98aa SACH *+,AR2 ; Store FR1 = Y = q/2 + d * sqrt(3) / 2.
201 ; ARP=AR2. AR0->FR2 AR2->q AR3->FR3
202 ;--------------------------------------------------------------------------------
203 003f 1fa8 LACC *+,15,AR0 ; ACCH = q/2.
204 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
205 ;--------------------------------------------------------------------------------
206 0040 be05 SPAC ; ACCH = q/2 - d * sqrt(3) / 2.
207 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:44 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
svgen_dq.asm PAGE 5
208 ;--------------------------------------------------------------------------------
209 0041 988b SACH *,AR3 ; Store FR2 = Z = q/2 - d * sqrt(3) / 2.
210 ; ARP=AR3. AR0->FR2 AR2->ta AR3->FR3.
211 ;--------------------------------------------------------------------------------
212 ;Sector calculations ("case statement")
213 ;--------------------------------------------------------------------------------
214 0042 10a0 LACC *+ ; Load sector #.
215 ; ARP=AR3. AR0->FR2 AR2->ta AR3->FR3.
216 ;--------------------------------------------------------------------------------
217 0043 bf90 ADD #SECTOR_TABLE_BASE
0044 00da'
218 ;--------------------------------------------------------------------------------
219 0045 a680 TBLR * ; FR3 = Sector subroutine address.
220 ; ARP=AR3. AR0->FR2 AR2->ta AR3->FR3.
221 ;--------------------------------------------------------------------------------
222 0046 1088 LACC *,AR0 ; ACC = Sector subroutine address.
223 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
224 ;--------------------------------------------------------------------------------
225 0047 be20 BACC ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
226 ;--------------------------------------------------------------------------------
227 ; Sector 0: this is special case for (Ualfa,Ubeta) = (0,0)
228 ;--------------------------------------------------------------------------------
229 0048 8b8a SECTOR_SR0: MAR *,AR2 ; ARP=AR2. AR0->FR2, AR2->ta, AR3->FR3.
230 ;--------------------------------------------------------------------------------
231 0049 aea0 SPLK #0,*+ ; ta = 0
004a 0000
232 ; ARP=AR2. AR0->FR2, AR2->tb, AR3->FR3.
233 ;--------------------------------------------------------------------------------
234 004b aea0 SPLK #0,*+ ; tb = 0
004c 0000
235 ; ARP=AR2. AR0->FR2, AR2->tc, AR3->FR3.
236 ;--------------------------------------------------------------------------------
237 004d ae90 SPLK #0,*- ; tc = 0
004e 0000
238 ; ARP=AR2. AR0->FR2, AR2->tb, AR3->FR3.
239 ;--------------------------------------------------------------------------------
240 004f 8b98 MAR *-,AR0 ; ARP=AR0. AR0->FR2, AR2->ta, AR3->FR3.
241 ;--------------------------------------------------------------------------------
242 0050 7980 B DUMMY ; ARP=AR0. AR0->FR2, AR2->ta, AR3->FR3.
0051 00d3'
243 ;--------------------------------------------------------------------------------
244 ; Sector Subroutine #1. On arrival :
245 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
246 ;--------------------------------------------------------------------------------
247 0052 109b SECTOR_SR1: LACC *-,AR3 ; ACC = Z
248 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
249 ;--------------------------------------------------------------------------------
250 0053 90a8 SACL *+,AR0 ; Store t1 = Z. ( FR3 = t1.)
251 ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR4.
252 ;--------------------------------------------------------------------------------
253 0054 108b LACC *,AR3 ; ACC = Y.
254 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
255 ;--------------------------------------------------------------------------------
256 0055 9090 SACL *- ; Store t2 = Y. ( FR4 = t2.)
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:44 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
svgen_dq.asm PAGE 6
257 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
258 ;--------------------------------------------------------------------------------
259 0056 bf80 LACC #7fffh ; ACCL= 1 (Q15).
0057 7fff
260 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
261 ;--------------------------------------------------------------------------------
262 0058 30a0 SUB *+ ; ACC = 1-t1.
263 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
264 ;--------------------------------------------------------------------------------
265 0059 309a SUB *-,AR2 ; ACC = 1-t1=t2.
266 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
267 ;--------------------------------------------------------------------------------
268 005a be0a SFR ; ACC = (1-t1=t2)/2.
269 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
270 ;--------------------------------------------------------------------------------
271 005b 8ba0 MAR *+ ; AR2++. Now AR2 -> tb
272 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR3.
273 ;--------------------------------------------------------------------------------
274 005c 909b SACL *-,AR3 ; Store tb
275 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
276 ;--------------------------------------------------------------------------------
277 005d 20aa ADD *+,AR2 ; ACC = tb + t1.
278 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
279 ;--------------------------------------------------------------------------------
280 005e 908b SACL *,AR3 ; Store ta = tb + t1.
281 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
282 ;--------------------------------------------------------------------------------
283 005f 208a ADD *,AR2 ; ACC = tb + t2.
284 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
285 ;--------------------------------------------------------------------------------
286 0060 7802 ADRK #2 ; Point AR2 to tc.
287 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
288 ;--------------------------------------------------------------------------------
289 0061 9090 SACL *- ; Store tc.
290 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
291 ;--------------------------------------------------------------------------------
292 0062 7980 B SV_POST_PROCESS
0063 00c6'
293 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
294 ;--------------------------------------------------------------------------------
295 ; Sector Subroutine #2. On arrival :
296 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
297 ;--------------------------------------------------------------------------------
298 0064 8b90 SECTOR_SR2: MAR *- ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR3.
299 ;--------------------------------------------------------------------------------
300 0065 109b LACC *-,AR3 ; ACC = Y
301 ; ARP=AR3. AR0->FR0 AR2->ta AR3->FR3.
302 ;--------------------------------------------------------------------------------
303 0066 90a8 SACL *+,AR0 ; Store t1 = Y. ( FR3 = t1.)
304 ; ARP=AR0. AR0->FR0 AR2->ta AR3->FR4.
305 ;--------------------------------------------------------------------------------
306 0067 10ab LACC *+,AR3 ; ACC = X.
307 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
308 ;--------------------------------------------------------------------------------
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:44 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
svgen_dq.asm PAGE 7
309 0068 be02 NEG ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
310 ;--------------------------------------------------------------------------------
311 0069 9090 SACL *- ; Store t2 = -X. ( FR4 = t2.)
312 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
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