📄 svgen_dq.lst
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dspa -l -s -i../include -v2xx -iD:/CCStudio_v3.1/c2400/cgtools/include -g svgen_dq.asm ../obj\svgen_dq.obj
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:44 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
svgen_dq.asm PAGE 1
1 ;=====================================================================================
2 ; File name: SVGEN_DQ.ASM
3 ;
4 ; Originator: Digital Control Systems Group
5 ; Texas Instruments
6 ;
7 ; Description:
8 ; This file contains source for Space vector modulation dq -> SV(a,b,c).
9 ;=====================================================================================
10 ; History:
11 ;-------------------------------------------------------------------------------------
12 ; 9-15-2000 Release Rev 1.00
13 ; 8-18-2003 Release Rev 3.10: Exit program safely for SECTOR0 and SECTOR7 (DUMMY location)
14 ; 3-27-2004 Release Rev 3.10: For the input pair (Ualfa,Ubeta)=(0,0), the (Ta,Tb,Tc) are (0,0,0),
15 ; not remain the same value as previously
16 ;================================================================================
17 ; Applicability: F240,F241,C242,F243,F24xx. (Peripheral Independant).
18 ;================================================================================
19 ; Routine Name: svgendq Routine Type: C Callable
20 ;
21 ; Description:
22 ;
23 ; C prototype : int svgendq(struct SVGENDQ *p);
24 ;
25 ; The struct is defined as follows:
26 ;
27 ; typedef struct SVGENDQ { int d,q,ta,tb,tc ; };
28 ;
29 ; Frame Usage Details:
30 ; | a | b | c | d
31 ;____________|_____________|_______________|____________|_____________
32 ; FR0 | va | X | X | X
33 ; FR1 | vb | Y | Y | Y
34 ; FR2 | vc | Z | Z | Z
35 ; FR3 | sector | sector | sr_address | t1
36 ; FR4 | | | | t2
37
38
39
40 ;================================================================================
41 .def _svgendq_calc
42 ;================================================================================
43 0005 __svgendq_framesize .set 0005h
44 ;================================================================================
45 0000 _svgendq_calc:
46 0000 8aa0 POPD *+
47 0001 80a0 SAR AR0,*+
48 0002 8180 SAR AR1,*
49 0003 b005 LARK AR0,__svgendq_framesize
50 0004 00e8 LAR AR0,*0+,AR0
51
52 ;================================================================================
53 0005 7c03 SBRK #3 ; Point AR0 to the first argument.
54 ;--------------------------------------------------------------------------------
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:44 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
svgen_dq.asm PAGE 2
55 0006 0280 LAR AR2,*
56 ; get the argument in AR2.
57 ; ARP=AR0. AR0->([FR0-3]=Argument 1) and AR2->d
58 0007 7803 ADRK #3 ; ARP=AR0. AR0->FR0 and AR2->d
59
60 0008 8b8a MAR *,AR2 ; ARP=AR2. AR0->FR0 and AR2->d
61 ;--------------------------------------------------------------------------------
62 0009 bf01 SPM 1 ; Set product shift mode to one.
63 ; ARP=AR2. AR0->FR0 and AR2->d
64 ;--------------------------------------------------------------------------------
65 000a be47 SETC SXM ; Turn sign extension mode on.
66 ; ARP=AR2. AR0->FR0 and AR2->d
67
68 ;--------------------------------------------------------------------------------
69 000b 7801 ADRK #1 ; ARP=AR2. AR0->FR0 and AR2->q
70 ;--------------------------------------------------------------------------------
71 000c 1098 LACC *-,AR0 ; Load q.
72 ; ARP=AR0. AR0->FR0 and AR2->d
73 ;--------------------------------------------------------------------------------
74 000d 90a0 SACL *+ ; Store va=q
75 ; ARP=AR0. AR0->FR1 and AR2->d
76 ;--------------------------------------------------------------------------------
77 000e ae80 SPLK #28377,*
000f 6ed9
78 ; FR1 = 0.5*qrt3.
79 ; ARP=AR0. AR0->FR1 and AR2->d
80 ;--------------------------------------------------------------------------------
81 0010 738a LT *,AR2 ; TREG = 0.5*qrt3.
82 ; ARP=AR2. AR0->FR1 and AR2->d
83 ;--------------------------------------------------------------------------------
84 0011 54a0 MPY *+ ; PREG = d * 0.5sqrt(3).
85 ; ARP=AR2. AR0->FR1 and AR2->q
86 ;--------------------------------------------------------------------------------
87 0012 b900 ZAC ; ACCH:ACCL=0.
88 ; ARP=AR2. AR0->FR1 and AR2->q
89 ;--------------------------------------------------------------------------------
90 0013 3f88 SUB *,15,AR0 ;ACC = -q/2
91 ; ARP=AR0. AR0->FR1 and AR2->q
92 ;--------------------------------------------------------------------------------
93 0014 be04 APAC ; ACC = -q/2 + d * 0.5sqrt(3)
94 ; ARP=AR0. AR0->FR1 and AR2->q
95 ;--------------------------------------------------------------------------------
96 0015 98a0 SACH *+ ; Store vb.
97 ; ARP=AR0. AR0->FR2 and AR2->q
98 ;--------------------------------------------------------------------------------
99 0016 be05 SPAC ; ACC = -q/2
100 ; ARP=AR0. AR0->FR2 and AR2->q
101 ;--------------------------------------------------------------------------------
102 0017 be05 SPAC ; ACC = -q/2 - (d * 0.5sqrt(3))
103 ; ARP=AR0. AR0->FR2 and AR2->q
104 ;--------------------------------------------------------------------------------
105 0018 98a0 SACH *+ ; Store vc.
106 ; ARP=AR0. AR0->FR3 and AR2->q
107 ;--------------------------------------------------------------------------------
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:44 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
svgen_dq.asm PAGE 3
108 0019 8080 SAR AR0,* ; FR3 = AR0 = &FR3.
109 ; ARP=AR0. AR0->FR3 and AR2->q
110 ;--------------------------------------------------------------------------------
111 001a 039b LAR AR3,*-,AR3
112 ; AR3 = FR3 = &FR3.
113 ; i.e. now AR3 points to FR3.
114 ; ARP=AR3. AR0->FR2 AR2->q AR3->FR3
115 ;--------------------------------------------------------------------------------
116 001b ae88 SPLK #0,*,AR0
001c 0000
117 ; Store sector = FR3 = 0
118 ; ARP=AR0. AR0->FR2 AR2->q AR3->FR3
119 ;--------------------------------------------------------------------------------
120 001d 1090 LACC *- ; Load vc.
121 ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
122 ;--------------------------------------------------------------------------------
123 001e e3cc BCND vref3_neg,LEQ
001f 0025'
124 ; If vc<0 then do not set bit 2 of sector.
125 ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
126 ;--------------------------------------------------------------------------------
127 0020 8b8b MAR *,AR3 ; ARP=AR3. AR0->FR1 AR2->q AR3->FR3
128 ;--------------------------------------------------------------------------------
129 0021 1080 LACC * ; Get sector code.
130 ; ARP=AR3. AR0->FR1 AR2->q AR3->FR3
131 ;--------------------------------------------------------------------------------
132 0022 bfc0 OR #4 ; Set bit 2.
0023 0004
133 ; ARP=AR3. AR0->FR1 AR2->q AR3->FR3
134 ;--------------------------------------------------------------------------------
135 0024 9088 SACL *,AR0 ; Store sector code
136 ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
137 ;--------------------------------------------------------------------------------
138 0025 1090 vref3_neg: LACC *- ; Load vb
139 ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
140 ;--------------------------------------------------------------------------------
141 0026 e3cc BCND vref2_neg,LEQ
0027 002d'
142 ; If vb<0 then do not set bit 1 of sector.
143 ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
144 ;--------------------------------------------------------------------------------
145 0028 8b8b MAR *,AR3 ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
146 ;--------------------------------------------------------------------------------
147 0029 1080 LACC * ; Get sector code.
148 ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
149 ;--------------------------------------------------------------------------------
150 002a bfc0 OR #2 ; Set bit 1.
002b 0002
151 ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
152 ;--------------------------------------------------------------------------------
153 002c 9088 SACL *,AR0 ; Store sector code
154 ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
155
156 002d 1080 vref2_neg: LACC * ; Load va
TMS320C24xx COFF Assembler Version 7.04 Fri May 04 19:50:44 2007
Copyright (c) 1987-2003 Texas Instruments Incorporated
svgen_dq.asm PAGE 4
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