📄 mlc.c
字号:
MLC_EraseBlock(1);
bufPt=(unsigned char *)0x31100000;
NFConDone_MLC=0, NFECCEncDone=0, NFECCDecDone=0;
rNFCONF = (rNFCONF & ~(1<<30))|(1<<24); // System Clock is more than 66Mhz, ECC type is MLC.
rNFCONT |= (1<<18); //ECC for programming.
rNFCONT|=(1<<9); // Enable RnB Interrupt
rNFCONT|=(1<<10); // Enable Illegal Access Interrupt
rNFCONT|=(1<<13); // Enable ECC encoding & decoding conpletion interrupt enable
rNFCONT|=(1<<12); // Enable ECC encoding & decoding conpletion interrupt enable
pISR_NFCON= (unsigned)NFCon_Int_MLC;
rSRCPND=BIT_NFCON;
rINTMSK&=~(BIT_NFCON);
/////////////////////////////////////////////////
// block1, page0 writing with valid data, ecc /
/////////////////////////////////////////////////
block=1;
page=0;
blockPage=(block<<7)+page;
NF_nFCE_L();
NF_CMD(0x0);//??????
NF_CMD(0x80); // Write 1st command
NF_ADDR(0); // Column (A[7:0]) = 0
NF_ADDR(0); // A[11:8]
NF_ADDR((blockPage)&0xff); // A[19:12]
NF_ADDR((blockPage>>8)&0xff); // A[27:20]
NF_ADDR((blockPage>>16)&0xff); // A[27:20]
// 0~511
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
// rNFCONT=0x43075;
for(i=0;i<512;i++) {
NF_WRDATA8(i); // Write one page to NFM from buffer
}
NF_MECC_Lock();
printf("1\n");
while(!(rNFSTAT&(1<<7))) ;
rNFSTAT|=(1<<7);
printf("2\n");
Mecc0 = rNFMECC0;
Mecc1 = rNFMECC1;
// 512~1023
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
for(i=512;i<1024;i++) {
NF_WRDATA8(i); // Write one page to NFM from buffer
}
while(!(rNFSTAT&(1<<7))) ;
rNFSTAT|=(1<<7);
printf("3\n");
Mecc2 = rNFMECC0;
Mecc3 = rNFMECC1;
// 1024~1535
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
for(i=1024;i<1536;i++) {
NF_WRDATA8(i); // Write one page to NFM from buffer
}
while(!(rNFSTAT&(1<<7))) ;
rNFSTAT|=(1<<7);
Mecc4 = rNFMECC0;
Mecc5 = rNFMECC1;
// 1536~2047
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
for(i=1536;i<2048;i++) {
NF_WRDATA8(i); // Write one page to NFM from buffer
}
while(!(rNFSTAT&(1<<7))) ;
rNFSTAT|=(1<<7);
printf("4\n");
Mecc6 = rNFMECC0;
Mecc7 = rNFMECC1;
// Get ECC data.
// Spare data for 8bit
// byte 0 1 2 3 4 5 6 7 8 9
// ecc [0] [1] [2] [3] [4] [5] [6]
MLC_Buf[1]=(U8)(Mecc0&0xff);
MLC_Buf[2]=(U8)((Mecc0>>8) & 0xff);
MLC_Buf[3]=(U8)((Mecc0>>16) & 0xff);
MLC_Buf[4]=(U8)((Mecc0>>24) & 0xff);
MLC_Buf[5]=(U8)(Mecc1&0xff);
MLC_Buf[6]=(U8)((Mecc1>>8) & 0xff);
MLC_Buf[7]=(U8)((Mecc1>>16) & 0xff);
MLC_Buf[8]=(U8)(Mecc2&0xff);
MLC_Buf[9]=(U8)((Mecc2>>8) & 0xff);
MLC_Buf[10]=(U8)((Mecc2>>16) & 0xff);
MLC_Buf[11]=(U8)((Mecc2>>24) & 0xff);
MLC_Buf[12]=(U8)(Mecc3&0xff);
MLC_Buf[13]=(U8)((Mecc3>>8) & 0xff);
MLC_Buf[14]=(U8)((Mecc3>>16) & 0xff);
MLC_Buf[15]=(U8)(Mecc4&0xff);
MLC_Buf[16]=(U8)((Mecc4>>8) & 0xff);
MLC_Buf[17]=(U8)((Mecc4>>16) & 0xff);
MLC_Buf[18]=(U8)((Mecc4>>24) & 0xff);
MLC_Buf[19]=(U8)(Mecc5&0xff);
MLC_Buf[20]=(U8)((Mecc5>>8) & 0xff);
MLC_Buf[21]=(U8)((Mecc5>>16) & 0xff);
MLC_Buf[22]=(U8)(Mecc6&0xff);
MLC_Buf[23]=(U8)((Mecc6>>8) & 0xff);
MLC_Buf[24]=(U8)((Mecc6>>16) & 0xff);
MLC_Buf[25]=(U8)((Mecc6>>24) & 0xff);
MLC_Buf[26]=(U8)(Mecc7&0xff);
MLC_Buf[27]=(U8)((Mecc7>>8) & 0xff);
MLC_Buf[28]=(U8)((Mecc7>>16) & 0xff);
for(i=0;i<64;i++) {
NF_WRDATA8(MLC_Buf[i]); // Write spare array(Main ECC)
MLC_Spare_Data[i]=MLC_Buf[i];
}
NF_CLEAR_RB();
NF_CMD(0x10); // Write 2nd command
NF_DETECT_RB();
// while(NFConDone_MLC==0);
rNFCONT&=~(1<<9);
rNFCONT&=~(1<<10); // Disable Illegal Access Interrupt
printf("5\n");
if(rNFSTAT&0x20)
{
printf("Illegal access Error\n");
return;
}
NF_CMD(0x70); // Read status command
for(i=0;i<3;i++); //twhr=60ns
if (NF_RDDATA8()&0x1) {// Page write error
NF_nFCE_H();
printf("first[PROGRAM_ERROR:block#=%d]\n",block);
return;
} else {
NF_nFCE_H();
}
/////////////////////////////////////////////////
// block1, page1 writing with invalid data, ecc /
/////////////////////////////////////////////////
NFConDone_MLC=0;
rSRCPND=BIT_NFCON;
rINTMSK=~(BIT_NFCON);
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
block=1;
page=1;
blockPage=(block<<7)+page;
NF_nFCE_L();
NF_CMD(0x0);//??????
NF_CMD(0x80); // Write 1st command
NF_ADDR(0); // Column 0
NF_ADDR(0); // Column 0
NF_ADDR(blockPage&0xff); //
NF_ADDR((blockPage>>8)&0xff); // Block & page num.
NF_ADDR((blockPage>>16)&0xff); //
//NF_RSTECC(); // Initialize ECC
printf("6\n");
#if 0 //No Error
for(i=0;i<512;i++) {
NF_WRDATA8(i);
}
#elif 1 //1-bit Error
for(i=0;i<512;i++) {
if(i==200) {
NF_WRDATA8(0xc0);
}
else {
NF_WRDATA8(i);
}
}
#elif 0 //2-bit Error
for(i=0;i<512;i++) {
if(i==128) {
NF_WRDATA8(129);
}
else if(i==255) {
NF_WRDATA8(0x7f);
}
else {
NF_WRDATA8(i);
}
}
#elif 0 //3-bit Error
for(i=0;i<512;i++) {
if(i==10) {
NF_WRDATA8(11);
}
else if(i==511) {
NF_WRDATA8(0xdf);
}
else if(i==128) {
NF_WRDATA8(0x82);
}
else {
NF_WRDATA8(i);
}
}
#elif 0 // 4-bit Error
for(i=0;i<512;i++) {
if(i==10) {
NF_WRDATA8(11);
}
else if(i==500) {
NF_WRDATA8(0xf0);
}
else if(i==200) {
NF_WRDATA8(0xc0);
}
else if(i==30) {
NF_WRDATA8(0x16);
}
else {
NF_WRDATA8(i);
}
}
#endif
while(!(rNFSTAT&(1<<7))) ;
//while(NFECCEncDone==0);
rNFSTAT|=(1<<7);
Mecc0 = rNFMECC0;
Mecc1 = rNFMECC1;
// 512~1023
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
for(i=512;i<1024;i++) {
NF_WRDATA8(i); // Write one page to NFM from buffer
}
while(!(rNFSTAT&(1<<7))) ;
rNFSTAT|=(1<<7);
Mecc2 = rNFMECC0;
Mecc3 = rNFMECC1;
// 1024~1535
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
for(i=1024;i<1536;i++) {
NF_WRDATA8(i); // Write one page to NFM from buffer
}
while(!(rNFSTAT&(1<<7))) ;
rNFSTAT|=(1<<7);
Mecc4 = rNFMECC0;
Mecc5 = rNFMECC1;
// 1536~2047
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
for(i=1536;i<2048;i++) {
NF_WRDATA8(i); // Write one page to NFM from buffer
}
while(!(rNFSTAT&(1<<7))) ;
rNFSTAT|=(1<<7);
Mecc6 = rNFMECC0;
Mecc7 = rNFMECC1;
for(i=0;i<64;i++) {
NF_WRDATA8(MLC_Buf[i]); // Write spare array(Main ECC)
MLC_Spare_Data[i]=MLC_Buf[i];
}
printf("7\n");
NF_CLEAR_RB();
NF_CMD(0x10); // Write 2nd command
NF_DETECT_RB();
//while(NFConDone_MLC==0);
rNFCONT&=~(1<<9);
rNFCONT&=~(1<<10); // Disable Illegal Access Interrupt
if(rNFSTAT&0x20) {
printf("Error\n");
return;
}
NF_CMD(0x70); // Read status command
for(i=0;i<30;i++); //twhr=60ns
if (NF_RDDATA8()&0x1) {// Page write error
NF_nFCE_H();
printf("Second[PROGRAM_ERROR:block#=%d]\n",block);
return;
} else {
NF_nFCE_H();
}
/////////////////////////////////////////////////
// block1, page1 reading with invalid data, ecc /
/////////////////////////////////////////////////
pISR_NFCON= (unsigned)NFCon_Int_MLC;
rSRCPND=BIT_NFCON;
rINTMSK&=~(BIT_NFCON);
block=1;
page=1;
blockPage=(block<<7)+page;
rNFCONF = (rNFCONF & ~(1<<30))|(1<<24); // System Clock is more than 66Mhz, ECC type is MLC.
rNFCONT &= ~(1<<18); //ECC for reading.
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
NF_nFCE_L();
NF_CLEAR_RB();
NF_CMD(0x00); // Read command
NF_ADDR(0); // Column (A[7:0]) = 0
NF_ADDR(0); // A[11:8]
NF_ADDR((blockPage)&0xff); // A[19:12]
NF_ADDR((blockPage>>8)&0xff); // A[27:20]
NF_ADDR((blockPage>>16)&0xff); // A[27:20]
NF_CMD(0x30); // 2'nd command
NF_DETECT_RB();
// rNFCONT=0x3045;
printf("8\n");
for(i=0;i<512;i++) {
*bufPt++=NF_RDDATA8(); // Read one page
}
// NF_MECC_Lock();
NF_CMD(0x05);
NF_ADDR((2048+1)&0xff); // 2060 = 0x080c
NF_ADDR(((2048+1)>>8)&0xff); // A[10:8]
NF_CMD(0xe0);
for(i=0;i<10;i++);
for(i=1;i<8;i++) {
MLC_Spare_Data[i]=NF_RDDATA8(); // Read one page
}
printf("9\n");
while(!(rNFSTAT&(1<<6)));
// while(NFECCDecDone==0);
rNFSTAT|=(1<<6);
printf("1st ECC check!\n");
if ((rNFECCERR0&(0x7<<26)) == 0x0){
printf("ECC OK!\n");
// return;
}
else {
printf("ECC FAIL!\n");
printf("status0:0x%x|status1:0x%x|bit:0x%x\n", rNFECCERR0, rNFECCERR1, rNFMLCBITPT);
// return;
}
// 512 ~ 1023
NF_RSTECC(); // Initialize ECC
// NF_MECC_UnLock();
NF_CMD(0x05);
NF_ADDR((512)&0xff); // 2060 = 0x080c
NF_ADDR(((512)>>8)&0xff); // A[10:8]
NF_CMD(0xe0);
for(i=0;i<10;i++);
for(i=0;i<512;i++) {
*bufPt++=NF_RDDATA8(); // Read one page
}
// NF_MECC_Lock();
NF_CMD(0x05);
NF_ADDR((2048+8)&0xff); // 2060 = 0x080c
NF_ADDR(((2048+8)>>8)&0xff); // A[10:8]
NF_CMD(0xe0);
for(i=0;i<10;i++);
for(i=8;i<15;i++) {
MLC_Spare_Data[i]=NF_RDDATA8(); // Read one page
}
while(!(rNFSTAT&(1<<6))) ;
// while(NFECCDecDone==0);
rNFSTAT|=(1<<6);
printf("2nd ECC check!\n");
if ((rNFECCERR0&(0x7<<26)) == 0x0){
printf("ECC OK!\n");
// return;
}
else {
printf("ECC FAIL!\n");
printf("status0:0x%x|status1:0x%x|bit:0x%x\n", rNFECCERR0, rNFECCERR1, rNFMLCBITPT);
// return;
}
// 1024 ~ 1535
NF_RSTECC(); // Initialize ECC
// NF_MECC_Lock();
NF_CMD(0x05);
NF_ADDR((1024)&0xff); // 2060 = 0x080c
NF_ADDR(((1024)>>8)&0xff); // A[10:8]
NF_CMD(0xe0);
for(i=0;i<10;i++);
for(i=0;i<512;i++) {
*bufPt++=NF_RDDATA8(); // Read one page
}
// NF_MECC_Lock();
NF_CMD(0x05);
NF_ADDR((2048+15)&0xff); // 2060 = 0x080c
NF_ADDR(((2048+15)>>8)&0xff); // A[10:8]
NF_CMD(0xe0);
for(i=0;i<10;i++);
for(i=15;i<22;i++) {
MLC_Spare_Data[i]=NF_RDDATA8(); // Read one page
}
while(!(rNFSTAT&(1<<6))) ;
// while(NFECCDecDone==0);
rNFSTAT|=(1<<6);
printf("3rd ECC check!\n");
if ((rNFECCERR0&(0x7<<26)) == 0x0){
printf("ECC OK!\n");
// return;
}
else {
printf("ECC FAIL!\n");
printf("status0:0x%x|status1:0x%x|bit:0x%x\n", rNFECCERR0, rNFECCERR1, rNFMLCBITPT);
// return;
}
// 1536 ~ 2047
NF_RSTECC(); // Initialize ECC
// NF_MECC_UnLock();
NF_CMD(0x05);
NF_ADDR((1536)&0xff); // 2060 = 0x080c
NF_ADDR(((1536)>>8)&0xff); // A[10:8]
NF_CMD(0xe0);
for(i=0;i<10;i++);
for(i=0;i<512;i++) {
*bufPt++=NF_RDDATA8(); // Read one page
}
// NF_MECC_Lock();
NF_CMD(0x05);
NF_ADDR((2048+22)&0xff); // 2060 = 0x080c
NF_ADDR(((2048+22)>>8)&0xff); // A[10:8]
NF_CMD(0xe0);
for(i=0;i<10;i++);
for(i=22;i<29;i++) {
MLC_Spare_Data[i]=NF_RDDATA8(); // Read one page
}
while(!(rNFSTAT&(1<<6))) ;
// while(NFECCDecDone==0);
rNFSTAT|=(1<<6);
printf("4th ECC check!\n");
if ((rNFECCERR0&(0x7<<26)) == 0x0){
printf("ECC OK!\n");
// return;
}
else {
printf("ECC FAIL!\n");
printf("status0:0x%x|status1:0x%x|bit:0x%x\n", rNFECCERR0, rNFECCERR1, rNFMLCBITPT);
// return;
}
NF_nFCE_H();
}
static void MLC_Init(void)
{
// for S3C2443
rNFCONF = (TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4);
// TACLS [14:12] CLE&ALE duration = HCLK*TACLS.
// TWRPH0 [10:8] TWRPH0 duration = HCLK*(TWRPH0+1)
// TWRPH1 [6:4] TWRPH1 duration = HCLK*(TWRPH1+1)
// AdvFlash(R) [3] Advanced NAND, 0:256/512, 1:1024/2048
// PageSize(R) [2] NAND memory page size
// when [3]==0, 0:256, 1:512 bytes/page.
// when [3]==1, 0:1024, 1:2048 bytes/page.
// AddrCycle(R) [1] NAND flash addr size
// when [3]==0, 0:3-addr, 1:4-addr.
// when [3]==1, 0:4-addr, 1:5-addr.
// BusWidth(R/W) [0] NAND bus width. 0:8-bit, 1:16-bit.
rNFCONT = (0<<17)|(0<<16)|(0<<10)|(0<<9)|(0<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<4)|(0x3<<1)|(1<<0);
// Lock-tight [17] 0:Disable lock, 1:Enable lock.
// Soft Lock [16] 0:Disable lock, 1:Enable lock.
// EnablillegalAcINT[10] Illegal access interupt control. 0:Disable, 1:Enable
// EnbRnBINT [9] RnB interrupt. 0:Disable, 1:Enable
// RnB_TrandMode[8] RnB transition detection config. 0:Low to High, 1:High to Low
// SpareECCLock [7] 0:Unlock, 1:Lock
// MainECCLock [6] 0:Unlock, 1:Lock
// InitMECC(W) [5] 1:Init main area ECC decoder/encoder.
// InitSECC(W) [4] 1:Init spare area ECC decoder/encoder.
// Reg_nCE1 [2] 0:nFCE=0, 1:nFCE=1.
// Reg_nCE0 [1] 0:nFCE=0, 1:nFCE=1.
// NANDC Enable [0] operating mode. 0:Disable, 1:Enable.
}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -