key.tan.rpt

这是一个凌阳单片机控制的红外键盘的控制程序

; N/A   ; None         ; 7.146 ns   ; KeyCode[0]~reg0  ; KeyCode[0]  ; CLK        ;
; N/A   ; None         ; 7.098 ns   ; KeyCode[7]~reg0  ; KeyCode[7]  ; CLK        ;
; N/A   ; None         ; 7.093 ns   ; KeyCode[4]~reg0  ; KeyCode[4]  ; CLK        ;
; N/A   ; None         ; 7.085 ns   ; KeyCode[6]~reg0  ; KeyCode[6]  ; CLK        ;
; N/A   ; None         ; 7.027 ns   ; KeyCode[11]~reg0 ; KeyCode[11] ; CLK        ;
; N/A   ; None         ; 7.008 ns   ; KeyCode[24]~reg0 ; KeyCode[24] ; CLK        ;
; N/A   ; None         ; 7.001 ns   ; KeyCode[19]~reg0 ; KeyCode[19] ; CLK        ;
; N/A   ; None         ; 6.948 ns   ; KeyCode[40]~reg0 ; KeyCode[40] ; CLK        ;
; N/A   ; None         ; 6.908 ns   ; KeyCode[18]~reg0 ; KeyCode[18] ; CLK        ;
; N/A   ; None         ; 6.905 ns   ; KeyCode[15]~reg0 ; KeyCode[15] ; CLK        ;
; N/A   ; None         ; 6.896 ns   ; KeyCode[38]~reg0 ; KeyCode[38] ; CLK        ;
; N/A   ; None         ; 6.881 ns   ; KeyCode[21]~reg0 ; KeyCode[21] ; CLK        ;
; N/A   ; None         ; 6.848 ns   ; KeyCode[37]~reg0 ; KeyCode[37] ; CLK        ;
; N/A   ; None         ; 6.827 ns   ; KeyCode[3]~reg0  ; KeyCode[3]  ; CLK        ;
; N/A   ; None         ; 6.792 ns   ; KeyCode[30]~reg0 ; KeyCode[30] ; CLK        ;
; N/A   ; None         ; 6.776 ns   ; KeyCode[39]~reg0 ; KeyCode[39] ; CLK        ;
; N/A   ; None         ; 6.774 ns   ; KeyCode[31]~reg0 ; KeyCode[31] ; CLK        ;
; N/A   ; None         ; 6.559 ns   ; KeyCode[28]~reg0 ; KeyCode[28] ; CLK        ;
; N/A   ; None         ; 6.466 ns   ; KeyCode[23]~reg0 ; KeyCode[23] ; CLK        ;
; N/A   ; None         ; 6.459 ns   ; KeyCode[36]~reg0 ; KeyCode[36] ; CLK        ;
+-------+--------------+------------+------------------+-------------+------------+


+------------------------------------------------------------------------------------+
; th                                                                                 ;
+---------------+-------------+-----------+----------+--------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From     ; To                 ; To Clock ;
+---------------+-------------+-----------+----------+--------------------+----------+
; N/A           ; None        ; -4.703 ns ; KeyPulse ; ChangeEdge:a|Sign  ; CLK      ;
; N/A           ; None        ; -4.704 ns ; KeyPulse ; ChangeEdge:a|Pulse ; CLK      ;
+---------------+-------------+-----------+----------+--------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Sep 05 21:31:11 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off KEY -c KEY --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 128.02 MHz between source register "Count[5]" and destination register "KeyCodeTemp[38]" (period= 7.811 ns)
    Info: + Longest register to register delay is 7.550 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y7_N6; Fanout = 5; REG Node = 'Count[5]'
        Info: 2: + IC(0.777 ns) + CELL(0.590 ns) = 1.367 ns; Loc. = LC_X18_Y7_N7; Fanout = 1; COMB Node = 'LessThan~540'
        Info: 3: + IC(0.426 ns) + CELL(0.590 ns) = 2.383 ns; Loc. = LC_X18_Y7_N6; Fanout = 1; COMB Node = 'LessThan~541'
        Info: 4: + IC(1.231 ns) + CELL(0.292 ns) = 3.906 ns; Loc. = LC_X18_Y8_N9; Fanout = 4; COMB Node = 'LessThan~542'
        Info: 5: + IC(0.777 ns) + CELL(0.114 ns) = 4.797 ns; Loc. = LC_X17_Y8_N5; Fanout = 42; COMB Node = 'KeyCodeTemp[0]~1773'
        Info: 6: + IC(1.886 ns) + CELL(0.867 ns) = 7.550 ns; Loc. = LC_X17_Y11_N2; Fanout = 2; REG Node = 'KeyCodeTemp[38]'
        Info: Total cell delay = 2.453 ns ( 32.49 % )
        Info: Total interconnect delay = 5.097 ns ( 67.51 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.781 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 112; CLK Node = 'CLK'
            Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X17_Y11_N2; Fanout = 2; REG Node = 'KeyCodeTemp[38]'
            Info: Total cell delay = 2.180 ns ( 78.39 % )
            Info: Total interconnect delay = 0.601 ns ( 21.61 % )
        Info: - Longest clock path from clock "CLK" to source register is 2.781 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 112; CLK Node = 'CLK'
            Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X17_Y7_N6; Fanout = 5; REG Node = 'Count[5]'
            Info: Total cell delay = 2.180 ns ( 78.39 % )
            Info: Total interconnect delay = 0.601 ns ( 21.61 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "ChangeEdge:a|Pulse" (data pin = "KeyPulse", clock pin = "CLK") is 4.756 ns
    Info: + Longest pin to register delay is 7.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_57; Fanout = 2; PIN Node = 'KeyPulse'
        Info: 2: + IC(5.547 ns) + CELL(0.478 ns) = 7.500 ns; Loc. = LC_X17_Y8_N7; Fanout = 22; REG Node = 'ChangeEdge:a|Pulse'
        Info: Total cell delay = 1.953 ns ( 26.04 % )
        Info: Total interconnect delay = 5.547 ns ( 73.96 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.781 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 112; CLK Node = 'CLK'
        Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X17_Y8_N7; Fanout = 22; REG Node = 'ChangeEdge:a|Pulse'
        Info: Total cell delay = 2.180 ns ( 78.39 % )
        Info: Total interconnect delay = 0.601 ns ( 21.61 % )
Info: tco from clock "CLK" to destination pin "KeyCode[26]" through register "KeyCode[26]~reg0" is 7.811 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.781 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469