key.map.rpt

这是一个凌阳单片机控制的红外键盘的控制程序

; Maximum Number of M512 Memory Blocks                               ; -1           ; -1            ;
; Maximum Number of M4K Memory Blocks                                ; -1           ; -1            ;
; Maximum Number of M-RAM Memory Blocks                              ; -1           ; -1            ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off          ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                 ; On           ; On            ;
+--------------------------------------------------------------------+--------------+---------------+


+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                     ;
+----------------------------------+-----------------+------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+------------------------------+
; KEY.v                            ; yes             ; User Verilog HDL File  ; E:/KEY/KEY.v                 ;
; ChangeEdge.v                     ; yes             ; Other                  ; E:/KEY/ChangeEdge.v          ;
+----------------------------------+-----------------+------------------------+------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 128     ;
; Total combinational functions     ; 85      ;
;     -- Total 4-input functions    ; 53      ;
;     -- Total 3-input functions    ; 5       ;
;     -- Total 2-input functions    ; 2       ;
;     -- Total 1-input functions    ; 25      ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 112     ;
; Total logic cells in carry chains ; 25      ;
; I/O pins                          ; 44      ;
; Maximum fan-out node              ; CLK     ;
; Maximum fan-out                   ; 112     ;
; Total fan-out                     ; 592     ;
; Average fan-out                   ; 3.44    ;
+-----------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |KEY                       ; 128 (126)   ; 112          ; 0           ; 44   ; 0            ; 16 (16)      ; 43 (42)           ; 69 (68)          ; 25 (25)         ; |KEY                ;
;    |ChangeEdge:a|          ; 2 (2)       ; 2            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 1 (1)            ; 0 (0)           ; |KEY|ChangeEdge:a   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 112   ;
; Number of registers using Synchronous Clear  ; 25    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 91    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |KEY|SquNumber[1]          ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |KEY|Sign[0]               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/KEY/KEY.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Sep 05 21:30:36 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off KEY -c KEY
Info: Found 1 design units, including 1 entities, in source file KEY.v
    Info: Found entity 1: KEY
Info: Elaborating entity "KEY" for the top level hierarchy
Info: Using design file ChangeEdge.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ChangeEdge
Info: Elaborating entity "ChangeEdge" for hierarchy "ChangeEdge:a"
Warning: Reduced register "Sign[1]" with stuck data_in port to stuck value GND
Info: Implemented 172 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 42 output pins
    Info: Implemented 128 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Sep 05 21:30:43 2006
    Info: Elapsed time: 00:00:07