📄 key.v
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module KEY(KeyPulse,CLK,KeyCode);
input KeyPulse;
input CLK;
output [41:0] KeyCode;
reg [41:0] KeyCode;
reg [41:0] KeyCodeTemp;
reg [18:0] Count;
reg [5:0] SquNumber;
reg [1:0] Sign;
wire Pulse;
ChangeEdge a(CLK,KeyPulse,Pulse);
always @(posedge CLK)
begin
if(Pulse)
begin
Count <= 19'd0;
if(Sign==0)//第一次进入
begin
Sign <= Sign+2'd1;
end
else//第一次进入后就将SIGN给你个恒大于0的数
begin
Sign <= 2'd1;
end
if(Sign>0)
begin
if(Count<100000)//为用户码或者数据码
begin
SquNumber <= SquNumber+6'd1;
KeyCodeTemp <= KeyCodeTemp >> 1;
if(Count<15000)//为0
begin
KeyCodeTemp[41] <= 1'b0;
end
else//为1
begin
KeyCodeTemp[41] <= 1'b1;
end
if(SquNumber==41)//解码完毕
begin
SquNumber <= 6'd0;
KeyCode <= KeyCodeTemp;
KeyCodeTemp <= 42'd0;
Sign <= 2'd0;
end
else//正在检测
begin
end
end//if(Count<100000)
else//为引导码
begin
SquNumber <= 6'd0;
end
end//if(Sign>0)
else
begin
end
end//if(Pulse)
else//PULSE为低,即处于2个下降沿,计数测时间
begin
Count <= Count+19'd1;
end
end//always
endmodule
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