key_pt_vhd.tcl

这是一个凌阳单片机控制的红外键盘的控制程序

## Copyright (C) 1991-2005 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions 
## and other software and tools, and its AMPP partner logic       
## functions, and any output files any of the foregoing           
## (including device programming or simulation files), and any    
## associated documentation or information are expressly subject  
## to the terms and conditions of the Altera Program License      
## Subscription Agreement, Altera MegaCore Function License       
## Agreement, or other applicable license agreement, including,   
## without limitation, that your use is for the sole purpose of   
## programming logic devices manufactured by Altera and sold by   
## Altera or its authorized distributors.  Please refer to the    
## applicable agreement for further details.

## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 5.0 Build 148 04/26/2005 SJ Full Version"

## DATE "09/05/2006 21:31:22"

## 
## Device: Altera EP1C3T144C8 Package TQFP144
## 

## 
## This Tcl script should be used for PrimeTime (VHDL) only
## 

## This file can be sourced in primetime

set report_default_significant_digits 3
set hierarchy_separator .

set quartus_root "c:/program files/quartus/quartus50/"
set search_path [list . [format "%s%s" $quartus_root "eda/synopsys/primetime/lib"]  ]

set link_path [list *  cyclone_asynch_io_lib.db cyclone_asynch_lcell_lib.db  cyclone_core_mem_lib.db cyclone_lcell_register_lib.db  cyclone_memory_register_lib.db  cyclone_pll_lib.db  alt_vtl.db]

read_vhdl  -vhdl_compiler  cyclone_all_pt.vhd 

##########################
## DESIGN ENTRY SECTION ##
##########################

read_vhdl  -vhdl_compiler KEY.vho
current_design KEY
link
## Set variable timing_propagate_single_condition_min_slew to false only for versions 2004.06 and earlier
regexp {([1-9][0-9][0-9][0-9]\.[0-9][0-9])} $sh_product_version dummy version
if { [string compare "2004.06" $version ] != -1 } {
   set timing_propagate_single_condition_min_slew false
}
set_operating_conditions -analysis_type single
read_sdf KEY_vhd.sdo

################################
## TIMING CONSTRAINTS SECTION ##
################################


## Start clock definition ##
# WARNING : The required clock period is not set. The default value (100 ns) is used 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { CLK } ] -name CLK  

set_propagated_clock [all_clocks]
## End clock definition ##

## Start create collections ##
## End create collections ##

## Start global settings ##
## End global settings ##

## Start collection commands definition ##

## End collection commands definition ##

## Start individual pin commands definition ##
## End individual pin commands definition ##

## Start Output pin capacitance definition ##
# Warning: using default load capacitance for LVTTL output port
set_load 10 [get_ports { KeyCode[0] KeyCode[1] KeyCode[2] KeyCode[3] KeyCode[4] KeyCode[5] KeyCode[6] KeyCode[7] KeyCode[8] KeyCode[9] KeyCode[10] KeyCode[11] KeyCode[12] \
    KeyCode[13] KeyCode[14] KeyCode[15] KeyCode[16] KeyCode[17] KeyCode[18] KeyCode[19] KeyCode[20] KeyCode[21] KeyCode[22] KeyCode[23] KeyCode[24] KeyCode[25] KeyCode[26] KeyCode[27] \
    KeyCode[28] KeyCode[29] KeyCode[30] KeyCode[31] KeyCode[32] KeyCode[33] KeyCode[34] KeyCode[35] KeyCode[36] KeyCode[37] KeyCode[38] KeyCode[39] KeyCode[40] KeyCode[41] } ]
## End Output pin capacitance definition ##

## Start clock uncertainty definition ##
## End clock uncertainty definition ##

## Start Multicycle and Cut Path definition ##
## End Multicycle and Cut Path definition ##

## Destroy Collections ##

update_timing