key.vho

这是一个凌阳单片机控制的红外键盘的控制程序

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 148 04/26/2005 SJ Full Version"

-- DATE "09/05/2006 21:31:21"

-- 
-- Device: Altera EP1C3T144C8 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cyclone;
USE IEEE.std_logic_1164.all;
USE cyclone.cyclone_components.all;

ENTITY 	KEY IS
    PORT (
	CLK : IN std_logic;
	KeyPulse : IN std_logic;
	KeyCode : OUT std_logic_vector(41 DOWNTO 0)
	);
END KEY;

ARCHITECTURE structure OF KEY IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_CLK : std_logic;
SIGNAL ww_KeyPulse : std_logic;
SIGNAL ww_KeyCode : std_logic_vector(41 DOWNTO 0);
SIGNAL CLK_acombout : std_logic;
SIGNAL KeyPulse_acombout : std_logic;
SIGNAL a_aSign : std_logic;
SIGNAL a_aPulse : std_logic;
SIGNAL Count_a0_a : std_logic;
SIGNAL Count_a0_a_a330 : std_logic;
SIGNAL Count_a0_a_a330COUT1_334 : std_logic;
SIGNAL Count_a1_a : std_logic;
SIGNAL Count_a1_a_a326 : std_logic;
SIGNAL Count_a1_a_a326COUT1_335 : std_logic;
SIGNAL Count_a2_a : std_logic;
SIGNAL Count_a2_a_a322 : std_logic;
SIGNAL Count_a2_a_a322COUT1_336 : std_logic;
SIGNAL Count_a3_a : std_logic;
SIGNAL Count_a3_a_a318 : std_logic;
SIGNAL Count_a4_a : std_logic;
SIGNAL Count_a4_a_a314 : std_logic;
SIGNAL Count_a4_a_a314COUT1_337 : std_logic;
SIGNAL Count_a5_a : std_logic;
SIGNAL Count_a5_a_a290 : std_logic;
SIGNAL Count_a5_a_a290COUT1_338 : std_logic;
SIGNAL Count_a6_a : std_logic;
SIGNAL Count_a6_a_a294 : std_logic;
SIGNAL Count_a6_a_a294COUT1_339 : std_logic;
SIGNAL Count_a7_a : std_logic;
SIGNAL Count_a7_a_a298 : std_logic;
SIGNAL Count_a7_a_a298COUT1_340 : std_logic;
SIGNAL Count_a8_a : std_logic;
SIGNAL Count_a8_a_a302 : std_logic;
SIGNAL Count_a9_a : std_logic;
SIGNAL Count_a9_a_a282 : std_logic;
SIGNAL Count_a9_a_a282COUT1_341 : std_logic;
SIGNAL Count_a10_a : std_logic;
SIGNAL Count_a10_a_a286 : std_logic;
SIGNAL Count_a10_a_a286COUT1_342 : std_logic;
SIGNAL Count_a11_a : std_logic;
SIGNAL Count_a11_a_a274 : std_logic;
SIGNAL Count_a11_a_a274COUT1_343 : std_logic;
SIGNAL Count_a12_a : std_logic;
SIGNAL Count_a12_a_a278 : std_logic;
SIGNAL Count_a12_a_a278COUT1_344 : std_logic;
SIGNAL Count_a13_a : std_logic;
SIGNAL Count_a13_a_a258 : std_logic;
SIGNAL Count_a14_a : std_logic;
SIGNAL Count_a14_a_a262 : std_logic;
SIGNAL Count_a14_a_a262COUT1_345 : std_logic;
SIGNAL Count_a15_a : std_logic;
SIGNAL Count_a15_a_a310 : std_logic;
SIGNAL Count_a15_a_a310COUT1_346 : std_logic;
SIGNAL Count_a16_a : std_logic;
SIGNAL Count_a16_a_a306 : std_logic;
SIGNAL Count_a16_a_a306COUT1_347 : std_logic;
SIGNAL Count_a17_a : std_logic;
SIGNAL Count_a17_a_a266 : std_logic;
SIGNAL Count_a17_a_a266COUT1_348 : std_logic;
SIGNAL Count_a18_a : std_logic;
SIGNAL LessThan_a543 : std_logic;
SIGNAL LessThan_a539 : std_logic;
SIGNAL LessThan_a540 : std_logic;
SIGNAL LessThan_a541 : std_logic;
SIGNAL LessThan_a542 : std_logic;
SIGNAL Sign_a0_a : std_logic;
SIGNAL SquNumber_a5_a_a139 : std_logic;
SIGNAL SquNumber_a0_a : std_logic;
SIGNAL SquNumber_a0_a_a153 : std_logic;
SIGNAL SquNumber_a0_a_a153COUT1_166 : std_logic;
SIGNAL SquNumber_a1_a : std_logic;
SIGNAL SquNumber_a1_a_a145 : std_logic;
SIGNAL SquNumber_a1_a_a145COUT1_167 : std_logic;
SIGNAL SquNumber_a2_a : std_logic;
SIGNAL SquNumber_a2_a_a149 : std_logic;
SIGNAL SquNumber_a2_a_a149COUT1 : std_logic;
SIGNAL SquNumber_a3_a : std_logic;
SIGNAL reduce_nor_a37 : std_logic;
SIGNAL SquNumber_a3_a_a157 : std_logic;
SIGNAL SquNumber_a4_a_a141 : std_logic;
SIGNAL SquNumber_a4_a_a141COUT1_168 : std_logic;
SIGNAL SquNumber_a5_a : std_logic;
SIGNAL reduce_nor_a1 : std_logic;
SIGNAL SquNumber_a1_a_a164 : std_logic;
SIGNAL SquNumber_a4_a : std_logic;
SIGNAL KeyCodeTemp_a1815 : std_logic;
SIGNAL KeyCodeTemp_a1818 : std_logic;
SIGNAL KeyCodeTemp_a1814 : std_logic;
SIGNAL KeyCodeTemp_a1816 : std_logic;
SIGNAL KeyCodeTemp_a1817 : std_logic;
SIGNAL KeyCodeTemp_a0_a_a1773 : std_logic;
SIGNAL KeyCodeTemp_a41_a : std_logic;
SIGNAL KeyCodeTemp_a40_a : std_logic;
SIGNAL KeyCodeTemp_a39_a : std_logic;
SIGNAL KeyCodeTemp_a38_a : std_logic;
SIGNAL KeyCodeTemp_a37_a : std_logic;
SIGNAL KeyCodeTemp_a36_a : std_logic;
SIGNAL KeyCodeTemp_a35_a : std_logic;
SIGNAL KeyCodeTemp_a34_a : std_logic;
SIGNAL KeyCodeTemp_a33_a : std_logic;
SIGNAL KeyCodeTemp_a32_a : std_logic;
SIGNAL KeyCodeTemp_a31_a : std_logic;
SIGNAL KeyCodeTemp_a30_a : std_logic;
SIGNAL KeyCodeTemp_a29_a : std_logic;
SIGNAL KeyCodeTemp_a28_a : std_logic;
SIGNAL KeyCodeTemp_a27_a : std_logic;
SIGNAL KeyCodeTemp_a26_a : std_logic;
SIGNAL KeyCodeTemp_a25_a : std_logic;
SIGNAL KeyCodeTemp_a24_a : std_logic;
SIGNAL KeyCodeTemp_a23_a : std_logic;
SIGNAL KeyCodeTemp_a22_a : std_logic;
SIGNAL KeyCodeTemp_a21_a : std_logic;
SIGNAL KeyCodeTemp_a20_a : std_logic;
SIGNAL KeyCodeTemp_a19_a : std_logic;
SIGNAL KeyCodeTemp_a18_a : std_logic;
SIGNAL KeyCodeTemp_a17_a : std_logic;
SIGNAL KeyCodeTemp_a16_a : std_logic;
SIGNAL KeyCodeTemp_a15_a : std_logic;
SIGNAL KeyCodeTemp_a14_a : std_logic;
SIGNAL KeyCodeTemp_a13_a : std_logic;
SIGNAL KeyCodeTemp_a12_a : std_logic;
SIGNAL KeyCodeTemp_a11_a : std_logic;
SIGNAL KeyCodeTemp_a10_a : std_logic;
SIGNAL KeyCodeTemp_a9_a : std_logic;
SIGNAL KeyCodeTemp_a8_a : std_logic;
SIGNAL KeyCodeTemp_a7_a : std_logic;
SIGNAL KeyCodeTemp_a6_a : std_logic;
SIGNAL KeyCodeTemp_a5_a : std_logic;
SIGNAL KeyCodeTemp_a4_a : std_logic;
SIGNAL KeyCodeTemp_a3_a : std_logic;
SIGNAL KeyCodeTemp_a2_a : std_logic;
SIGNAL KeyCodeTemp_a1_a : std_logic;
SIGNAL KeyCodeTemp_a0_a : std_logic;
SIGNAL KeyCode_a0_a_a83 : std_logic;
SIGNAL KeyCode_a0_a_areg0 : std_logic;
SIGNAL KeyCode_a1_a_areg0 : std_logic;
SIGNAL KeyCode_a2_a_areg0 : std_logic;
SIGNAL KeyCode_a3_a_areg0 : std_logic;
SIGNAL KeyCode_a4_a_areg0 : std_logic;
SIGNAL KeyCode_a5_a_areg0 : std_logic;
SIGNAL KeyCode_a6_a_areg0 : std_logic;
SIGNAL KeyCode_a7_a_areg0 : std_logic;
SIGNAL KeyCode_a8_a_areg0 : std_logic;
SIGNAL KeyCode_a9_a_areg0 : std_logic;
SIGNAL KeyCode_a10_a_areg0 : std_logic;
SIGNAL KeyCode_a11_a_areg0 : std_logic;
SIGNAL KeyCode_a12_a_areg0 : std_logic;
SIGNAL KeyCode_a13_a_areg0 : std_logic;
SIGNAL KeyCode_a14_a_areg0 : std_logic;
SIGNAL KeyCode_a15_a_areg0 : std_logic;
SIGNAL KeyCode_a16_a_areg0 : std_logic;
SIGNAL KeyCode_a17_a_areg0 : std_logic;
SIGNAL KeyCode_a18_a_areg0 : std_logic;
SIGNAL KeyCode_a19_a_areg0 : std_logic;
SIGNAL KeyCode_a20_a_areg0 : std_logic;
SIGNAL KeyCode_a21_a_areg0 : std_logic;
SIGNAL KeyCode_a22_a_areg0 : std_logic;
SIGNAL KeyCode_a23_a_areg0 : std_logic;
SIGNAL KeyCode_a24_a_areg0 : std_logic;
SIGNAL KeyCode_a25_a_areg0 : std_logic;
SIGNAL KeyCode_a26_a_areg0 : std_logic;
SIGNAL KeyCode_a27_a_areg0 : std_logic;
SIGNAL KeyCode_a28_a_areg0 : std_logic;
SIGNAL KeyCode_a29_a_areg0 : std_logic;
SIGNAL KeyCode_a30_a_areg0 : std_logic;
SIGNAL KeyCode_a31_a_areg0 : std_logic;
SIGNAL KeyCode_a32_a_areg0 : std_logic;
SIGNAL KeyCode_a33_a_areg0 : std_logic;
SIGNAL KeyCode_a34_a_areg0 : std_logic;
SIGNAL KeyCode_a35_a_areg0 : std_logic;
SIGNAL KeyCode_a36_a_areg0 : std_logic;
SIGNAL KeyCode_a37_a_areg0 : std_logic;
SIGNAL KeyCode_a38_a_areg0 : std_logic;
SIGNAL KeyCode_a39_a_areg0 : std_logic;
SIGNAL KeyCode_a40_a_areg0 : std_logic;
SIGNAL KeyCode_a41_a_areg0 : std_logic;

BEGIN

ww_CLK <= CLK;
ww_KeyPulse <= KeyPulse;
KeyCode <= ww_KeyCode;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

CLK_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_CLK,
	combout => CLK_acombout);

KeyPulse_aI : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_KeyPulse,
	combout => KeyPulse_acombout);

a_aSign_aI : cyclone_lcell
-- Equation(s):
-- a_aSign = DFFEAS(!KeyPulse_acombout, GLOBAL(CLK_acombout), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F0F",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	datac => KeyPulse_acombout,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => a_aSign);

a_aPulse_aI : cyclone_lcell
-- Equation(s):
-- a_aPulse = DFFEAS(!KeyPulse_acombout & !a_aSign, GLOBAL(CLK_acombout), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "000F",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	datac => KeyPulse_acombout,
	datad => a_aSign,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => a_aPulse);

Count_a0_a_aI : cyclone_lcell
-- Equation(s):
-- Count_a0_a = DFFEAS(!Count_a0_a, GLOBAL(CLK_acombout), VCC, , , , , a_aPulse, )
-- Count_a0_a_a330 = CARRY(Count_a0_a)
-- Count_a0_a_a330COUT1_334 = CARRY(Count_a0_a)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "55AA",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	dataa => Count_a0_a,
	aclr => GND,
	sclr => a_aPulse,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => Count_a0_a,
	cout0 => Count_a0_a_a330,
	cout1 => Count_a0_a_a330COUT1_334);

Count_a1_a_aI : cyclone_lcell
-- Equation(s):
-- Count_a1_a = DFFEAS(Count_a1_a $ (Count_a0_a_a330), GLOBAL(CLK_acombout), VCC, , , , , a_aPulse, )
-- Count_a1_a_a326 = CARRY(!Count_a0_a_a330 # !Count_a1_a)
-- Count_a1_a_a326COUT1_335 = CARRY(!Count_a0_a_a330COUT1_334 # !Count_a1_a)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "5A5F",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	dataa => Count_a1_a,
	aclr => GND,
	sclr => a_aPulse,
	cin0 => Count_a0_a_a330,
	cin1 => Count_a0_a_a330COUT1_334,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => Count_a1_a,
	cout0 => Count_a1_a_a326,
	cout1 => Count_a1_a_a326COUT1_335);

Count_a2_a_aI : cyclone_lcell
-- Equation(s):
-- Count_a2_a = DFFEAS(Count_a2_a $ !Count_a1_a_a326, GLOBAL(CLK_acombout), VCC, , , , , a_aPulse, )
-- Count_a2_a_a322 = CARRY(Count_a2_a & !Count_a1_a_a326)
-- Count_a2_a_a322COUT1_336 = CARRY(Count_a2_a & !Count_a1_a_a326COUT1_335)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "C30C",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	datab => Count_a2_a,
	aclr => GND,
	sclr => a_aPulse,
	cin0 => Count_a1_a_a326,
	cin1 => Count_a1_a_a326COUT1_335,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => Count_a2_a,
	cout0 => Count_a2_a_a322,
	cout1 => Count_a2_a_a322COUT1_336);

Count_a3_a_aI : cyclone_lcell
-- Equation(s):
-- Count_a3_a = DFFEAS(Count_a3_a $ Count_a2_a_a322, GLOBAL(CLK_acombout), VCC, , , , , a_aPulse, )
-- Count_a3_a_a318 = CARRY(!Count_a2_a_a322COUT1_336 # !Count_a3_a)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "3C3F",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	datab => Count_a3_a,
	aclr => GND,
	sclr => a_aPulse,
	cin0 => Count_a2_a_a322,
	cin1 => Count_a2_a_a322COUT1_336,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => Count_a3_a,
	cout => Count_a3_a_a318);

Count_a4_a_aI : cyclone_lcell
-- Equation(s):
-- Count_a4_a = DFFEAS(Count_a4_a $ !Count_a3_a_a318, GLOBAL(CLK_acombout), VCC, , , , , a_aPulse, )
-- Count_a4_a_a314 = CARRY(Count_a4_a & !Count_a3_a_a318)