moore-fsm.v

来自「10010序列检测」· Verilog 代码 · 共 70 行

module  MOOREfsm(clk,rst,a,z);
input clk,rst;
input a;
output z;

reg z;
reg [2:0]  state,nextstate;
 
 parameter  S0=3'b000;
 parameter  S1=3'b001; 
 parameter  S2=3'b010; 
 parameter  S3=3'b011;  
 parameter  S4=3'b100;
 parameter  S5=3'b101;

 always @(posedge clk or negedge rst)
           if  (!rst)  
                            state <= S0;  
                           
        else  
        									  state <= nextstate; 

 
 
 always@(rst or state or a)
 			if(!rst)
 						z=0;
 			else
 			       case(state)
 			       S0:
 			      	  begin
 			      	  		z=0;
 			      	  		nextstate=(a==1)?S1:S0; 			      	  
 			       		end
 			       S1:
 			        begin
 			      	  		z=0;
 			      	  		nextstate=(a==0)?S2:S1; 			      	  
 			       		end
 			       S2:
 			        begin
 			      	  		z=0;
 			      	  		nextstate=(a==0)?S3:S1; 			      	  
 			       		end
 			       S3:
 			        begin
 			      	  		z=0;
 			      	  		nextstate=(a==1)?S4:S0; 			      	  
 			       		end
 			       S4:
 			        begin
 			      	  		z=0;
 			      	  		nextstate=(a==0)?S5:S1; 			      	  
 			       		end
 			       S5:
 			        begin
 			      	  		z=1;
 			      	  		nextstate=(a==0)?S3:S1; 			      	  
 			       		end
 			             		
 			       default:
 			        begin
 			      	  		z=0;
 			      	  		nextstate=S0; 			      	  
 			       	end
 			       	
 			    endcase
 
 
 endmodule