mealy-fsm.v

来自「10010序列检测」· Verilog 代码 · 共 78 行

module  MEALYfsm(clk,rst,a,z);
input clk,rst;
input a;
output z;

reg z;
reg [3:0]  state,nextstate;

reg    temp;
 
 parameter  S0=4'b0000;
 parameter  S1=4'b0001; 
 parameter  S2=4'b0010; 
 parameter  S3=4'b0011;  
 parameter  S4=4'b0100;


 always @(posedge clk or negedge rst)
           if  (!rst)  
                            state <= S0;  
                           
        else  
        								 state <= nextstate; 
        								 
        								 
 always@(posedge clk or negedge rst)
    if(!rst)  z<=0;
    else
      begin
       if((temp==1)&&(nextstate==S2))
         z<=1;
       else z<=0;  
     end          

 

 always@(rst or state or a)
 			if(!rst)
 						temp=0;
 			else
 			       case(state)
 			       S0:
 			      	  begin
 			      	  		temp=0;
 			      	  		nextstate=(a==1)?S1:S0; 			      	  
 			       		end
 			       S1:
 			        begin
 			      	  		temp=0;
 			      	  		nextstate=(a==0)?S2:S1; 			      	  
 			       		end
 			       S2:
 			        begin
 			      	  		temp=0;
 			      	  		nextstate=(a==0)?S3:S1; 			      	  
 			       		end
 			       S3:
 			        begin
 			      	  		temp=0;
 			      	  		nextstate=(a==1)?S4:S0; 			      	  
 			       		end
 			       S4:
 			        begin
 			        
 			         	nextstate=(a==0)?S2:S1;
 			          temp=(a==0)?1:0; 	
 			      	  			      	  
 			       		end
 			      			             		
 			       default:
 			        begin
 			      	  		temp=0;
 			      	  		nextstate=S0; 			      	  
 			       	end
 			    endcase
 
 
 endmodule