divide5.v

来自「这是一个五分频电路设计」· Verilog 代码 · 共 82 行

/*
module divide5error(rst,clk,clk5);
	input rst,clk;
	output clk5;	
	reg clk5;
	reg [2:0] counter;		
always @(clk or rst)
		if (!rst)
			 counter <=3'b000;
		else if(counter==3'b100)
			     counter <=3'b000;
		else        counter <= counter+1;
		
  always @(rst or counter)
		 if (!rst)
			 clk5=1'b0;
		else if(counter==3'b100)
             clk5=~clk5;
endmodule
   */

 /*
module divide5error(rst,clk,clk5);
	input rst,clk;
	output clk5;	
	reg clk5;
	reg [2:0] counter;		
always @(posedge clk or negedge clk or  negedge rst)
		if (!rst)
			 counter <=3'b000;
		else if(counter==3'b100)
			counter <=3'b000;
		else        counter <= counter+1;
		
  always @(rst or counter)
  if (!rst)
			 clk5=1'b0;
		else if(counter==3'b100)
             clk5=~clk5;
endmodule

*/



module divide5error(rst,clk,clk5);
	input rst,clk;
	output clk5;	
	
	//reg clk5;
	
	reg [2:0] counter;		
	wire clk_;
	reg clk_temp1,clk_temp2;
	
	assign clk_=~clk;
	assign clk5=clk_temp1|clk_temp2;
	
always @(posedge clk or  negedge rst)
		if (!rst)
			 counter <=3'b000;
		else if(counter==3'b100)
			counter <=3'b000;
		else        counter <= counter+1;
		
  always @(posedge clk or  negedge rst)
  if (!rst)
			 clk_temp1=1'b0;
		else if((counter==3'b010)||(counter==3'b100))
             clk_temp1=~clk_temp1;
  
  always @(posedge clk_ or  negedge rst)
  if (!rst)
			 clk_temp2=1'b0;
		else
             clk_temp2<=clk_temp1;
endmodule