📄 psk_moden.mdl
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Model {
Name "psk_moden"
Version 5.0
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ExecutionOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Sun Mar 19 18:14:55 2006"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "oldslam"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Wed Apr 05 21:28:35 2006"
ModelVersionFormat "1.%<AutoIncrement:9>"
ConfigurationManager "None"
SimParamPage "Solver"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "ode45"
SolverMode "Auto"
StartTime "0.0"
StopTime "5000"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints on
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
RTWInlineParameters off
BlockReductionOpt on
BooleanDataType on
ConditionallyExecuteInputs on
ParameterPooling on
OptimizeBlockIOStorage on
ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType DiscretePulseGenerator
PulseType "Sample based"
Amplitude "1"
Period "2"
PulseWidth "1"
PhaseDelay "0"
SampleTime "1"
VectorParams1D on
}
Block {
BlockType Scope
Floating off
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "0"
}
Block {
BlockType "S-Function"
FunctionName "system"
PortCounts "[]"
SFunctionModules "''"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "psk_moden"
Location [127, 96, 1139, 736]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "GND"
Ports [0, 1]
Position [315, 161, 330, 179]
ForegroundColor "blue"
ShowName off
SourceBlock "bus_alteradspbuilder/GND"
SourceType "SGND AlteraBlockSet"
ncstsamp "1"
}
Block {
BlockType Reference
Name "GND1"
Ports [0, 1]
Position [310, 51, 325, 69]
ForegroundColor "blue"
ShowName off
SourceBlock "bus_alteradspbuilder/GND"
SourceType "SGND AlteraBlockSet"
ncstsamp "1"
}
Block {
BlockType Reference
Name "Increment\nDecrement"
Ports [2, 1]
Position [365, 138, 420, 182]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Increment\nDecrement"
SourceType "IncDec AlteraBlockSet"
BusType "Unsigned Integer"
bwl "8"
bwr "4"
direction "Increment"
cst_display "0"
cst "0"
clken on
MaskValue "1"
ntsamp "-1"
}
Block {
BlockType Reference
Name "Increment\nDecrement1"
Ports [2, 1]
Position [365, 28, 420, 72]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Increment\nDecrement"
SourceType "IncDec AlteraBlockSet"
BusType "Unsigned Integer"
bwl "8"
bwr "4"
direction "Increment"
cst_display "0"
cst "0"
clken on
MaskValue "1"
ntsamp "-1"
}
Block {
BlockType Reference
Name "Input"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [200, 97, 265, 113]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Input Port"
bwl "1"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input"
ppat "d:\\matlab6p5\\work\\fsk\\DSPBuilder_fsk_moden"
nSgCpl "0"
}
Block {
BlockType Reference
Name "LUT"
Ports [1, 1]
Position [460, 140, 550, 180]
ForegroundColor "blue"
SourceBlock "gate_alteradspbuilder/LUT"
SourceType "LUT AlteraBlockSet"
BusType "Signed Integer"
bwl "8"
bwr "0"
bwaddr "8"
MatlabArray "127*sin( [0:2*pi/(2^8):2*pi] )"
LocPin "psk_modenLUT"
lpm on
modulename "c:\\documents and settings\\oldslam\\桌面\\dsp_"
"homework\\psk\\DSPBuilder_psk_moden\\psk_modenLUT.lut"
pipeline off
IslibDir "0"
clken off
}
Block {
BlockType Reference
Name "LUT1"
Ports [1, 1]
Position [460, 30, 550, 70]
ForegroundColor "blue"
SourceBlock "gate_alteradspbuilder/LUT"
SourceType "LUT AlteraBlockSet"
BusType "Signed Integer"
bwl "8"
bwr "0"
bwaddr "8"
MatlabArray "-127*sin( [0:2*pi/(2^8):2*pi] )"
LocPin "psk_modenLUT1"
lpm on
modulename "c:\\documents and settings\\oldslam\\桌面\\dsp_"
"homework\\psk\\DSPBuilder_psk_moden\\psk_modenLUT1.lut"
pipeline off
IslibDir "0"
clken off
}
Block {
BlockType Reference
Name "NOT"
Ports [1, 1]
Position [300, 32, 340, 48]
ForegroundColor "blue"
SourceBlock "gate_alteradspbuilder/NOT"
SourceType "LogiBit AlteraBlockSet"
Operator "NOT"
Inputs "2"
}
Block {
BlockType Reference
Name "Output1"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [715, 102, 780, 118]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Output"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Output Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Output"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Parallel \nAdder Subtractor"
Ports [2, 1]
Position [640, 62, 675, 138]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
SourceType "Sum AlteraBlockSet"
Inputs "2"
direction "++"
pipeline on
clken off
MaskValue "1"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator"
Position [20, 88, 65, 122]
PulseType "Time based"
Period "1024"
PulseWidth "50"
}
Block {
BlockType Scope
Name "Scope"
Ports [3]
Position [860, 16, 920, 184]
Location [5, 60, 1029, 741]
Open off
NumInputPorts "3"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
axes3 "%<SignalLabel>"
}
List {
ListType SelectedSignals
axes1 ""
axes2 ""
axes3 ""
}
YMin "-5~-5~-5"
YMax "5~5~5"
DataFormat "StructureWithTime"
MaxDataPoints "50000"
}
Line {
SrcBlock "Increment\nDecrement"
SrcPort 1
DstBlock "LUT"
DstPort 1
}
Line {
SrcBlock "Input"
SrcPort 1
Points [0, 0; 10, 0]
Branch {
Points [0, 45]
DstBlock "Increment\nDecrement"
DstPort 1
}
Branch {
Points [0, -65]
DstBlock "NOT"
DstPort 1
}
}
Line {
SrcBlock "GND"
SrcPort 1
DstBlock "Increment\nDecrement"
DstPort 2
}
Line {
SrcBlock "Increment\nDecrement1"
SrcPort 1
DstBlock "LUT1"
DstPort 1
}
Line {
SrcBlock "LUT1"
SrcPort 1
Points [0, 0; 40, 0]
Branch {
Points [0, 30]
DstBlock "Parallel \nAdder Subtractor"
DstPort 1
}
Branch {
Points [250, 0]
DstBlock "Scope"
DstPort 1
}
}
Line {
SrcBlock "NOT"
SrcPort 1
DstBlock "Increment\nDecrement1"
DstPort 1
}
Line {
SrcBlock "GND1"
SrcPort 1
DstBlock "Increment\nDecrement1"
DstPort 2
}
Line {
SrcBlock "LUT"
SrcPort 1
Points [40, 0; 0, -40; 25, 0]
Branch {
DstBlock "Parallel \nAdder Subtractor"
DstPort 2
}
Branch {
Points [0, -20]
DstBlock "Scope"
DstPort 2
}
}
Line {
SrcBlock "Parallel \nAdder Subtractor"
SrcPort 1
Points [0, 10]
DstBlock "Output1"
DstPort 1
}
Line {
SrcBlock "Output1"
SrcPort 1
Points [0, 45]
DstBlock "Scope"
DstPort 3
}
Line {
SrcBlock "Pulse\nGenerator"
SrcPort 1
DstBlock "Input"
DstPort 1
}
}
}
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