amccpci.asc

详细介绍了一篇关于pci开发的接口芯片

      minimum grant register is in 250-ns increments
      assuming a clock rate of 33 Mhz.


      Also see:  ^Editing Keys^, ^Maximum Latency^
*E

*B 21,Maximum Latency

                     Maximum Latency
                     ---------------

      This field may be optionally used by bus-masters
      to specify how often this device needs PCI bus
      access.  A value of zero indicates that the bus
      master has no stringent requirement.  The units
      defined by the maximum latency register is in
      250-ns increments assuming a clock rate of 33 Mhz.


      Also see:  ^Editing Keys^, ^Minimum Grant^
*E

*B 22,Expansion ROM Size

                  Expansion ROM Size
                  ------------------

      This field defines a mechanism for assigning
      a space within physical memory for an expansion
      ROM.  Access from the PCI bus to the memory
      space defined by this field will cause one or
      more accesses to the S59XX controller's
      external BIOS ROM (or nvRAM) interface.


      Also see:  ^Editing Keys^
*E

*B 23,Edit Base Addresses

                   Edit Base Addresses
                   -------------------

      This menu item allows editing of the Base Address
      Registers (BADR0 - BADR4).  These registers are
      utilized to provide a mechanism for assigning
      memory or I/O space for the add-on.
*E

*B 24,Edit Other Configuration Registers

             Edit Other Configuration Registers
             ----------------------------------

      This menu item allows editing of all Configuration
      Registers except the Base Address Registers or
      Register 45 (S5933 only).

*E

*B 25,Exit Menu

                       Exit Menu
                       ---------

       This menu item will exit the current menu
       and return the program back to the previous
       menu.
*E

*B 26,Edit Location 45 Configuration Bits

              Edit Location 45 Configuration Bits
              -----------------------------------

       This menu item will allow editing of the Location
       45 Configuration bits.  These options include
       Bus-master, Synchronous FIFO Operation and PCI
       Latency Timer Timeout controls.
*E

*B 27,Save Filetype


                      Save Filetype
                      -------------

       Choose the file type of the resulting saved image.
       The choices are Intel Hex or Binary formats.

*E

*B 28,Save Filename

                        Save Filename
                        -------------

     Enter filename to save the current memory image to.
*E

*B 29,Display Memory Image

                  Display Memory Image
                  --------------------

      This menu item will display the current memory
      image in Hexidecimal format.


      Also see:  ^Global Help^
*E

*B 30,Select Load Location

                      Select Load Location
                      --------------------

     Select where to load the PCI memory image from.  The
     image may be loaded from a PCI device or a binary or
     Intel Hex file.
*E

*B 31,Select File

                         Select File
                         -----------

     Select a file to load a memory image from.
*E

*B 32,Select Base Address

                      Select Base Address
                      -------------------

     This menu is used to select a specific Base Address
     to edit.

     Also see: ^Edit Base Addresses^
*E

*B 33,Base Address Type

                        Base Address Type
                        -----------------

     This field is used to specify whether the base address
     is to be assigned to Memory or I/O Space.  You may
     also select to disable Base Addresses BADR1 - BADR4.
*E

*B 34,Memory Location

                    Base Address Memory Location
                    ----------------------------

     This field specifies whether the Base Address may be
     located anywhere in 32-bit memory space or must be
     restricted to the first megabyte of memory space.
*E

*B 35,Prefetchable

                          Prefetchable
                          ------------

     This field specifies whether the region of memory may
     be cached.  A device can mark memory prefetchable if
     there are no side effects on reads, the device returns
     all bytes on reads regardless of the byte enables, and
     host bridges can merge processor writes without causing
     errors
*E

*B 36,Base Memory Size

                       Base Memory Size
                       ----------------

     This field is used to specify the size of the memory
     region defined by the base address.
*E

*B 37,Pass Through

                        Pass Through
                        ------------

      This field specifies the add-on interface's width
      behavior for the memory region defined by the
      base address.  The pass-through width may be
      either 32, 16 or 8 bits.  The base address register
      may also be disabled with this field.
*E

*B 38,Bus Master Control

                       Bus Master Control
                       ------------------

      This field specifies where the bus master control
      is sourced.  The bus master may be controlled from
      either the add-on or the PCI interface.
*E

*B 39,RDFIFO Control

                         RDFIFO Control
                         --------------

     This field specifies whether the RDFIFO pin is
     an enable rather than a clock.  The Synchronous
     FIFO transfer mode greatly assists high performance
     reading from the FIFO by maintaining valid data
     outputs throughout the entire clock period.
*E

*B 40,WRFIFO Control

                         WRFIFO Control
                         --------------

     This field specifies whether the WRFIFO pin is
     an enable rather than a clock.  The Synchronous
     FIFO transfer mode greatly assists high performance
     reading from the FIFO by maintaining valid data
     outputs throughout the entire clock period.
*E

*B 41,Load PCI Device

                        Load PCI Device
                        ---------------

     Selection of this menu item will display a list
     of PCI devices to load a memory image from.
*E

*B 42,Load File

                       Load from File
                       --------------

      Selection of this menu item will display a list
      of files to load a memory image from.
*E

*B 43,Merge File

                        Merge File
                        ----------

      Selection of this menu item will display a list
      of Intel Hex filenames to merge the current
      memory image with.
*E

*B 44,Save File

                        Save File
                        ---------

      Selection of this menu item will allow saving
      the current memory image to a Binary or Intel
      Hex file.
*E

*B 45,NvBuild

              Non-volatile Memory Builder
              ---------------------------

      Selection of this menu item will allow you to
      build a non-volatile memory image that may be
      loaded into an AMCC PCI Controller.

*E

*B 46,Target Latency Timer Control

             Target Latency Timer Control
             ----------------------------

     This field specifies whether the Target Latency
     timer is enabled.  If this field is enabled, the
     PCI Latency Timer will be PCI 2.1 compliant.  If
     disabled, the device will not disconnect w/retry
     if cannot issue TRDY in specified time.

*E

*B 47,Subsystem Vendor ID

             Subsystem Vendor ID
             -------------------


*E

*B 48,Subsystem Device ID

             Subsystem Device ID
             -------------------

*E

*B 49,RDRETRY Control

                         RDRETRY Control
                         --------------

     Need to fill this part in!
*E

*B 50,WRMODE Control

                         WRMODE Control
                         --------------

     Need to fill this part in!
*E