amcclib.c

详细介绍了一篇关于pci开发的接口芯片

*/
UINT8 reg_read8(UINT32 base, UINT32 offset)
{
UINT8 amt;

	check_base(base);
    if (base & 1)  /* I/O location */
      amt = inp((UINT16)offset + (UINT16)(base & 0xFFFFFFFCL));
    else
      amt = xpeek8((base & 0xFFFFFFF0L) + offset);
    return(amt);
}

/* REG_READ16 - Read word from register (memory or I/O) from region base 

	Entry:	base - base register as read from PCI (includes memory/IO bit)
			offset - offset from base to register
	Return:	data read
*/
UINT16 reg_read16(UINT32 base, UINT32 offset)
{
UINT16 amt;

	check_base(base);
    if (base & 1)  /* I/O location */
      amt = inpw((UINT16)offset + (UINT16)(base & 0xFFFFFFFCL));
    else
      amt = xpeek16((base & 0xFFFFFFF0L) + offset);
    return(amt);
}

UINT32 reg_read32(UINT32 base, UINT32 offset)
{
UINT32 amt;

	check_base(base);
    if (base & 1)  /* I/O location */
      amt = inpl((UINT16)offset + (UINT16)(base & 0xFFFFFFFCL));
    else
      amt = xpeek32((base & 0xFFFFFFF0L) + offset);
    return(amt);
}


/* 	RESET_NVRAM_CONFIGURATION - reset the structure to defaults 

	Zeros out all nvram including the BIOS portion, then sets
	up values:
	The defaults are:
		BIOS ROM valid signature bytes
		BIOS rom length 512
*/
void reset_nvram_configuration(struct nv_space *nvram)
{

  /* initialize */
  memset(nvram,0,sizeof(*nvram));	/* 0-fill */
  nvram->sig = 0x55AA;				/* valid ROM signature bytes */
  nvram->len=1;						/* 512 bytes (per 1) */
  nvram->init_entry=0;				/* BIOS entry point for init */
  nvram->pci_ptr=0x80;   			/* ROM offset for pci data structure */

	/* configuration load image (starts at $40) */
  nvram->ven_id = 0x10e8;			/* the default */
  nvram->dev_id=0x5920;				/* the default */
  nvram->rev_id=0;
  nvram->class[2] = 0xFF;
  nvram->base[0] = 0x10E8FFC1L;   	/* required base (C1 can differ) */
  nvram->int_line = 0xFF;
  nvram->int_pin = 0x01;
}


/* CONFIGURE_NVRAM_REGION - setsup the region in nvram */
void configure_nvram_region(struct nv_space *nvram, struct region *reg)
{
int i;

    i = reg->num;
    if (reg->io_mem) {   /* config as I/O */
       nvram->base[i] = (reg->size & 0xFFFFFFFCL) + 0x01;
    }
    else {  /* config as mem */
       nvram->base[i] = (reg->size & 0xFFFFFFF0L) + ((reg->loc & 3) << 1) + ((reg->prefetch & 1) << 3);
    }
}


void nvram_add_bios(struct nv_space *nvram, void *bios, UINT16 len )
/* 	Merge in bios image to nv ram struct.
	Copies vendor and device ID from nvRAM into PCI structure in BIOS since
	they must match. Also sets up nvRAM for 2k BIOS.

	Entry:	nvram - nvRAM image address 0
			bios - BIOS address 0
			len	- #bytes from 
*/
{
unsigned int i;
UINT8 *pt, *pbios;
UINT16 pci_data_structure;

  	pt = (UINT8 *)nvram;
	pbios = (UINT8 *)bios;

	// copy bios to nvram buffer...
  	for (i=0; i<len; i++)
  	{
  		if ( (i < 0x40) || (i > 0x7F) )	// skip 5920 config
	      	pt[i] = pbios[i];

    }

	// enable 2k BIOS...
	*(UINT32 *)(&pt[0x70]) = 0xFFFFF801L;
	// copy VID, DID from config portion to PCI data structure...
	pci_data_structure = *(UINT16 *)(&pt[0x18]);
	*(UINT32 *)(&pt[pci_data_structure + 4]) = *(UINT32 *)( &pt[0x40] );
//	*(UINT16 *)(&pt[pci_data_structure + 4]) = swapword( *(UINT16 *)(&pt[0x40]) );
//	*(UINT16 *)(&pt[pci_data_structure + 6]) = swapword( *(UINT16 *)(&pt[0x42]) );
}


/*  CHECKSUM
	compute a byte checksum
*/
UINT8 checksum(UINT8 *data, UINT16 len)
{
UINT16 i;
UINT8 ch = 0;

  for( i = 0; i < len; i++) 
    ch += data[i];
	return ch;
}


int nvram_wait(UINT32 base)
/*
	Return:	NVRAM_OK if goes not busy before timeout, else
			NVRAM_TIMEOUT and errstring updated.

	1-2 second timeout
*/
{
	time_t start, now;

	time( &start );
	while( TRUE )
    {
    	if ( (reg_read8(base,OFF_NV_CTL) & 0x80) == 0 )
    		return NVRAM_OK;
		time ( &now );
		if ( difftime(now, start) > 2 )
			return NVRAM_TIMEOUT;
	}

}


/* NVRAM_READ - read from nv_ram */
int nvram_read(UINT8 *nvram, int offset, int len, UINT32 base, \
	int chip_type )
/* 	
	Entry:	*nvram - where to place the data
			offset - offset (relative address) into NVRAM to start read
		 	len - length (in bytes) to read
		 	base - Operational register base address for AMCC chip

 	Returns: NVRAM_x (see lib.h), errstring updated if error
*/
{
	int i, result;

  	for (i=0;i<len;i++) 
  	{
  		result = nvram_read8(base, i+offset, nvram, chip_type);
    	if ( result != NVRAM_OK )
	      	return result;
		nvram++;
  	}

  	return( NVRAM_OK );
}

/* NVRAM_WRITE - write buffer to NVRAM

	Entry:	*nvram - buffer pointer
			offset - offset (relative address) into NVRAM to start writing
			len - length (in bytes) to write
			base - Operational register base address for AMCC chip

 	Returns: NVRAM_x (see lib.h), errstring updated if error
*/
int nvram_write(UINT8 *nvram, int offset, int len, UINT32 base, \
	int chip_type)
{
	int i, result;

	/* had *nvram, then nvram++ */
  	for (i=0; i<len; i++) 
  	{
		result = nvram_write8(base, i+offset, nvram[i], chip_type);
    	if ( result != NVRAM_OK )
	      	return result;
  	}

  	return( NVRAM_OK );
}


/* NVRAM_READ8 - read a byte from nv_ram

 	Returns: NVRAM_x (see lib.h)
*/
int nvram_read8(UINT32 base, UINT16 nvaddr, UINT8 *data, int chip_type )
{
	int status;

  	status = nvram_wait(base);
  	if ( status != NVRAM_OK ) return NVRAM_READ_TIMEOUT;
  	/* write low address */
  	reg_write8(base, OFF_NV_CTL, NVCTL_LOWADD);
  	reg_write8(base, OFF_NV_DATA,nvaddr&0xff);
  	/* write high address */
  	reg_write8(base, OFF_NV_CTL, NVCTL_HIADD);
  	reg_write8(base, OFF_NV_DATA, nvaddr >> 8);
  	/* NV command */
  	reg_write8(base, OFF_NV_CTL, NVCTL_READ);
  	status = nvram_wait(base);
  	if ( status != NVRAM_OK ) return NVRAM_READ_TIMEOUT;
  	*data = reg_read8(base, OFF_NV_DATA);

	check_nvram_type(chip_type); 			// see if type is valid
	if ( chip_type != AMCC_5933 )
		// check for nv op error...
		if (NVCTL_ERROR & reg_read8(base,OFF_NV_CTL))
			return( NVRAM_READ_ERROR );

	return( NVRAM_OK );
}


/* NVRAM_WRITE8 - write a byte to nv_ram
 	Returns: NVRAM_x (see lib.h)
*/
int nvram_write8(UINT32 base, UINT16 nvaddr, UINT8 amt, int chip_type)
{
	int status;

  	status = nvram_wait(base);
  	if ( status != NVRAM_OK ) return NVRAM_WRITE_TIMEOUT;
  	/* write low address */
  	reg_write8(base, OFF_NV_CTL, NVCTL_LOWADD);
  	reg_write8(base, OFF_NV_DATA, nvaddr&0xff);
  	/* write high address */
  	reg_write8(base, OFF_NV_CTL, NVCTL_HIADD);
  	reg_write8(base, OFF_NV_DATA, nvaddr >> 8);
  	reg_write8(base, OFF_NV_CTL, 0);	/* latch it */
  	/* WRITE Data */
  	reg_write8(base, OFF_NV_DATA, amt);
  	/* NV command */
  	reg_write8(base, OFF_NV_CTL, NVCTL_WRITE);
  	status = nvram_wait(base);
  	if ( status != NVRAM_OK ) return NVRAM_WRITE_TIMEOUT;

	check_nvram_type(chip_type);		// see if type is valid
	if ( chip_type == AMCC_5933 )		// requires delay
 		delay_ms( (UINT16)XDELAY_MS );
	else // if !5933, check the error bit...
	{
		if ( NVCTL_ERROR & reg_read8(base,OFF_NV_CTL) )
			return( NVRAM_WRITE_ERROR );
	}

	return( NVRAM_OK );
}

/* 	BUFFER_STORE - Write file - 0 = OK, 1 = FAIL 
	binary write of "len" bytes.

	Return:	0 if OK, else <> is error code.
*/
int buffer_store(char *filename, void *buffer, int len)
{
   FILE *out;

   if ((out = fopen(filename, "wb")) == NULL) 
   {
     fprintf(stderr, "Cannot open output file \"%s\".\n", filename);
     return 1;
   }

   while (!ferror(out) && len ) {
     fputc(*((unsigned char *)buffer), out);
     ((unsigned char *)buffer)++;
     len--;
   }
   if (ferror(out))
   {
	    fprintf(stderr, "Error writing file \"%s\".\n", filename);
     	return 1;
   }
   
   fclose(out);
   return 0;
}


/* BUFFER_LOAD - read file - 0 = OK, 1 = file error, 2 = file too small 
	binary read of "len" bytes. File length must be >= request, or an
	error will occur.

	Return:	0 if OK, else <> is error code.
*/
int buffer_load(char *filename, void *buffer, int len)
{
   FILE *in;

   if ((in = fopen(filename, "rb")) == NULL) {
     fprintf(stderr, "Cannot open input file \"%s\".\n", filename );
     return 1;
   }

   while (!ferror(in) && !feof(in) && len ) {
     *((unsigned char *)buffer) = fgetc(in);
     ((unsigned char *)buffer)++;
     len--;
   }
   if (ferror(in))
   {
	    fprintf(stderr, "File error reading %s.\n", filename);
     	return 1;
   }

   fclose(in);
   if (len)   /* file too small */
	{
	    fprintf(stderr, "File \"%s\" is smaller than requested load length.\n", filename);
        return 2;
	}
   return 0;
}

static void check_base( UINT32 base )
{
	if ( base == 0 )
	{
		fprintf( stderr, "Error - called register function with \"base\" = 0.\n" );
		exit(1);
	}
}

static void check_nvram_type( int chip_type )
// see if type is valid
{
	if ( (chip_type == AMCC_5920)
		 || (chip_type == AMCC_5933)
       )  ;
	else
	{
		fprintf( stderr, "Programming error. \"chip_type\" %4.4x not set correctly.\n", \
		chip_type );
		exit(1);
	}
}

/*
#define CONFIG_READ_DWORD 0

int read_config_dword( UINT8 bus_number, UINT8 device_and_function, \
	UINT8 register_number, UINT32*data32 )
{
	int ret_status;

	ret_status = read_config_area( CONFIG_READ_DWORD, 0, 0, 0, data32 );
	return ret_status;