lib.c

详细介绍了一篇关于pci开发的接口芯片

				exit(1);
		}
	}	

	return num_regions;
}

int region_waits( int region )
/*	
	Return:	current region #wait states from PTCR

	Use this function instead of getting directly from the structure.
	This encapsulates the method used for easier mods.
*/
{
	int shift = (region - 1) * 8;
	UINT32 data32 = region_read32( &chip_uut, 0L, PTCR );

	data32 = data32 >> shift;	
	data32 &= 7;
	return (int)data32;
}



VOID region_make_fifo( int region )
/*
	set up region for FIFO (control reg)
	set up width bits in control reg to match current nvram info
	(assumes current width data in NVRAM is same as last uut reset)
	set up to not use PTADR (valid in active mode only).

	Leaves Endian conversion and write fifo enable alone.
*/
{
	int shift = (region - 1) * 8;

	// clear bit 20+ in control reg to select FIFO...
	UINT32 data32 = 0x100000L << (region-1);
	bclr_control_reg(data32);

	// set PTADR as not used...
	bclr_region32( &chip_uut, 0L, PTCR, 0x80L << shift );
	region_set_width( region );
	region_set_waits( region, region_waits(region) );
}


VOID region_make_sram( int region )
/*
	set up region for SRAM
	set up width bits in control reg to match current nvram info
	(assumes current width data in NVRAM is same as last uut reset)
	set up to use PTADR (valid in active mode only).

	Leaves Endian conversion and write fifo enable alone.
*/
{
	int shift = (region - 1) * 8;

	// set bit in control reg to select SRAM...
	UINT32 data32 = 0x100000L << (region-1);
	bset_control_reg(data32);
		
	// set PTADR as used...
	bset_region32( &chip_uut, 0L, PTCR, 0x80L << shift );
	region_set_width( region );
	region_set_waits( region, region_waits(region) );
}


void region_set_waits( int region, int waits )
/* 	Set up PTCR and testboard with desired wait states.

	Entry:	region has been configured as SRAM or FIFO
*/
{
	int shift;

	waits &= 7;
	if ( region_is_sram(region) )
	if ( active_mode() && (waits < MIN_SRAM_WAITS_ACTIVE) )
		waits = MIN_SRAM_WAITS_ACTIVE;
	if ( !active_mode() && (waits < MIN_SRAM_WAITS_PASSIVE) )
		waits = MIN_SRAM_WAITS_PASSIVE;

	// do PTCR...
	shift = (region - 1) * 8;
	bclr_region32( &chip_uut, 0L, PTCR, 7L << shift );
	bset_region32( &chip_uut, 0L, PTCR, ((UINT32)waits) << shift );

	// do testboard...
	if ( region_is_sram(region) )
	{
		set_sram_waits( waits );
		// set PTADR...
		bset_region32( &chip_uut, 0, PTCR, 0x80L << shift );
	}
	else
	{
		set_fifo_waits( waits );
		// clear PTADR...
		bclr_region32( &chip_uut, 0, PTCR, 0x80L << shift );
	}
}

void set_fifo_waits( int waits )
/* set up control register wait state bits */
{
	control &= ~( 7L << 11 );		// drop the 3 control bits
	bset_control_reg( ((UINT32)waits) << 11 );
}


void set_sram_waits( int waits )
/* set up control register wait state bits */
{
	if ( active_mode() && (waits < MIN_SRAM_WAITS_ACTIVE) )
		waits = MIN_SRAM_WAITS_ACTIVE;
	if ( !active_mode() && (waits < MIN_SRAM_WAITS_PASSIVE) )
		waits = MIN_SRAM_WAITS_PASSIVE;

	control &= ~( 7L << 8 ); 		// drop the 3 control bits
	bset_control_reg( ((UINT32)waits) << 8 );
}

void region_set_width( int region )
/*	
	Set width on testboard based on nvram width
	and region type.

	Entry:	region selected as SRAM or FIFO
*/
{
	int shift;
	
	if ( region_is_sram(region) )
		shift = 18;
	else
		shift = 16;

	bclr_control_reg( 3L << shift );	// zero the bits
	switch( region_width(region) )
	{
		case 8:
			bset_control_reg( 1L << shift );
			return;
		case 16:
			bset_control_reg( 2L << shift );
			return;
		default:
			bset_control_reg( 3L << shift );
			return;
	}

}


int region_is_sram( int region )
/*
	Return:	TRUE if region is configured as SRAM

	Bit 20 is lowest region bit, set means SRAM
*/
{
	int shift = 8 * (region - 1);
	UINT32 mask =  0x100000L << (region - 1), ptcr;

	ptcr = region_read32( &chip_uut, 0L, PTCR ) >>  shift;
	if ( 	( (control & mask)  &&  !(ptcr & 0x80L) )
		||	( !(control & mask) &&  (ptcr & 0x80L) )
		)
	{
		fprintf( stderr, "Control register and PTCR setup of region %d\n" \
			"are not consistent for selecting SRAM/FIFO.\n", region );
		exit(1);
	}

	if ( ptcr & 0x80L )  return TRUE;
	return FALSE;
}

int region_get_prefetch_size( int region )
{
	UINT32 data32;
	int data;

	data32 = region_read32( &chip_uut, 0L, PTCR );
	data32 = data32 >> (8 * (region-1));
	data32 &= 0xFFL;
	data = (int)data32;
	return ((data >> 3) & 3 );
}

VOID region_set_prefetch_size( int region, int size )
/*
	Set up prefetch size.
*/
{
	int shift = 3 + ((region - 1) * 8);

	if ( size > 3 )
	{
		fprintf( stderr, "Called region_set_prefetch_size with size > 3.\n" );
		exit(1);
	}
	bclr_region32( &chip_uut, 0L, PTCR, 3L << shift );
	bset_region32( &chip_uut, 0L, PTCR, (UINT32)size << shift );
	reset_uut_fifo();	// clear anything still there
}


VOID region_write_fifo_enable( int region )
// enable writeback FIFO
{
	UINT32 data32 = 0x20L << ((region-1) * 8);
	bclr_region32( &chip_uut, 0, PTCR, data32 );
}

VOID region_write_fifo_disable( int region )
// disable writeback FIFO
{
	UINT32 data32 = 0x20L << ((region-1) * 8);
	bset_region32( &chip_uut, 0, PTCR, data32 );
}


int region_little_endian( int region )
{
	UINT32 data32;
	int shift = (region - 1) * 8;

	data32 = region_read32( &chip_uut, 0L, PTCR );
	if ( data32 & (0x40L << shift) )  return FALSE;
	return TRUE;
}

void region_make_little_endian( int region )
{
	UINT32 data32;
	int shift = (region - 1) * 8;

	data32 = region_read32( &chip_uut, 0L, PTCR );
	data32 &= ~(0x40L << shift);
	region_write32( &chip_uut, 0L, PTCR, data32 );
}

void region_make_big_endian( int region )
{
	UINT32 data32;
	int shift = (region - 1) * 8;

	data32 = region_read32( &chip_uut, 0L, PTCR );
	data32 |= (0x40L << shift);
	region_write32( &chip_uut, 0L, PTCR, data32 );
}

VOID reset_uut_fifo( VOID )
// reset 5920 internal FIFO
{
	bset_region32( &chip_uut, 0, RCR, 0x02000000L );
}


int program_base_addresses ( UINT32 base0, UINT32 base1, UINT32 base2, \
				UINT32 base3, UINT32 base4 )
/*
	!!!!!!!!!!!!!!!!!!
		CAREFUL
	!!!!!!!!!!!!!!!!!!
	You must program base addresses with values that are multiples of 
	the region size (power-of-two).

	Program all 5 base address registers...

	Entry:	addresses to use. If 0, does not modify base address.
	Return:	PCI_X (PCI_SUCCESSFUL is OK)
*/
{
	int status = PCI_SUCCESSFUL;

	if ( base0 != 0L )
	{
		status = pci_config_write32( &chip_uut, PCI_CS_BASE_ADDRESS_0, base0  );
		if ( status != PCI_SUCCESSFUL )  return status;
	}

	if ( base1 != 0L )
	{
		status = pci_config_write32( &chip_uut, PCI_CS_BASE_ADDRESS_1, base1  );
		if ( status != PCI_SUCCESSFUL )  return status;
	}

	if ( base2 != 0L )
	{
		status = pci_config_write32( &chip_uut, PCI_CS_BASE_ADDRESS_2, base2  );
		if ( status != PCI_SUCCESSFUL )  return status;
	}

	if ( base3 != 0L )
	{
		status = pci_config_write32( &chip_uut, PCI_CS_BASE_ADDRESS_3, base3  );
		if ( status != PCI_SUCCESSFUL )  return status;
	}

	if ( base4 != 0L )
	{
		status =  pci_config_write32( &chip_uut, PCI_CS_BASE_ADDRESS_4, base4  );
		if ( status != PCI_SUCCESSFUL )  return status;
	}

	return status;
}


VOID data_fifo_reset( VOID )
/*	Reset, unreset testboard data FIFO.
*/
{
	bclr_control_reg( CTRL_FIFORST );
	bset_control_reg( CTRL_FIFORST );
}


int data_fifo_empty( VOID )
/*
	Return:	TRUE if data FIFO is empty.
*/
{
	if ( read_status_register() & STAT_EFL ) return FALSE;
	return TRUE;
}

int data_fifo_full( VOID )
/*
	Return:	TRUE if data FIFO is empty.
*/
{
	if ( read_status_register() & STAT_FFL ) return FALSE;
	return TRUE;
}

int fifo_size_bytes( int region )
/*
	Return:	size of FIFO in bytes (16-bit = /2, 8-bit = /4)
*/
{
	switch( region_width( region ) )
	{
		case 8:		return FIFO_SIZE_BYTES / 4;
		case 16:	return FIFO_SIZE_BYTES / 2;
		case 32:	return FIFO_SIZE_BYTES;
		default:
			printf( "Programming error in fifo_size_bytes.\n" );
			exit(1);
	}

	return 0;
}

int sram_size_bytes( int region )
/*
	Return:	size of SRAM in bytes (16-bit = /2, 8-bit = /4)
*/
{
	switch( region_width( region ) )
	{
		case 8:		return SRAM_SIZE_BYTES / 4;
		case 16:	return SRAM_SIZE_BYTES / 2;
		case 32:	return SRAM_SIZE_BYTES;
		default:
			printf( "Programming error in sram_size_bytes.\n" );
			exit(1);
	}

	return 0;
}

int active_mode( VOID )
{
	if ( read_status_register() & (UINT32)STAT_PTMODE ) return FALSE;
	return TRUE;
}


int get_contiguous_regions( UINT32 min_region0_size, UINT32 max_region0_size, \
	UINT32 min_region1_size, UINT32 max_region1_size, \
	int *reg0, int *reg1, int flags )
/*
	Finds two contiguous regions.

	Note: Currently does not distinguiush I/O and memory addresses,
		but no test asks for contiguous addresses of different types.

	Entry:	min_regionX_size - minimum size of region X
			max_regionX_size - maximum size of region X
			regX - where to return the region number
			flags - CONT_REGx_MEMORY
					CONT_REGx_IO

	Return:	TRUE if find them

	Each region can request MEMORY and/or IO
*/
{
	int region, found, region0, region1;
	UINT32 region_base[MAX_PT_REGION + 1], addr0, addr1;

	if 	(  ( !flags & (CONT_REG0_MEMORY | CONT_REG0_IO) )
		|| ( !flags & (CONT_REG1_MEMORY | CONT_REG1_IO) )
		)
	{
		fprintf( stderr, "Error calling get_contiguous_regions().\n"
					"Variable \"flags\" does not define memory or I/O.\n" );
		exit(1);
	}


	// get addresses for all regions throwing out non-type addresses...
	for( region =  MIN_PT_REGION; region <=  MAX_PT_REGION; region ++ )
	{
		if ( flags & CONT_REG0_MEMORY )
		{
			if ( region_is_memory(region) )
				region_base[region] = chip_uut.reg[region].base;
			else
				region_base[region] = 0L;
		}

		else	// is I/O
		{
			if ( !region_is_memory(region) )
				region_base[region] = chip_uut.reg[region].base;
			else
				region_base[region] = 0L;
		}

	}

	// put the addresses in order...
	qsort( &region_base[MIN_PT_REGION], \
		 (size_t)(MAX_PT_REGION - MIN_PT_REGION + 1), 4, dword_compare );

	// find contiguous of correct size
	for( region =  MIN_PT_REGION; region <  MAX_PT_REGION; region ++ )
	{
		region0 = find_region( region_base[region] );
		if ( region0 == 0xFF )  continue;
		region1 = find_region( region_base[region + 1] );
		addr0 = chip_uut.reg[region0].base & 0xFFFFFFF0L;
		addr1 = chip_uut.reg[region1].base & 0xFFFFFFF0L;
		if ( region_size(region0) < min_region0_size )  continue;
		if ( region_size(region0) > max_region0_size )  continue;
		if ( region_size(region1) < min_region1_size )  continue;
		if ( region_size(region1) > max_region1_size )  continue;
		if ( addr1 != addr0 + region_size(region0)  )
			continue;  		// not contiguous
		found = TRUE;
		break;
	}

	if ( !found )  return FALSE;
	*reg0 = region0;
	*reg1 = region1;
	return TRUE;
}

static int find_region( UINT32 base )
/*
	Match base to a UUT base address

	Return:	region# that matches (else 0xFF)
*/
{
	int region;

	for( region = MIN_PT_REGION; region <=  MAX_PT_REGION; region++ )
	{
		if ( chip_uut.reg[region].base == base )
			return region;
	}

	return 0xFF;
}



static int dword_compare( const void *data0, const void *data1 )
{
	if ( *(UINT32 *)data0 == *(UINT32 *)data1 ) return 0;
	if ( *(UINT32 *)data0 < *(UINT32 *)data1 ) return -1;
	return 1;
}