iolpc3100.h

uCOSII 在LPC3180上的移植代码

/* FIFO counter register */
typedef struct{
  __REG32 DataCount         :15;
  __REG32                   :17;
} __SD_FIFOCnt_bits;

/* I2C RX/TX Data FIFO */
typedef union{
  //I2Cx_RX
  struct {
    __REG32 RxData          : 8;
    __REG32                 :24;
  };
  //I2Cx_TX
  struct {
    __REG32 TxData          : 8;
    __REG32 START           : 1;
    __REG32 STOP            : 1;
    __REG32                 :22;
  };
} __i2c_rx_tx_bits;

/* I2C Status Register */
typedef struct{
  __REG32 TDI               : 1;
  __REG32                   : 1;
  __REG32 NAI               : 1;
  __REG32 DRMI              : 1;
  __REG32                   : 1;
  __REG32 ACTIVE            : 1;
  __REG32 SCL               : 1;
  __REG32 SDA               : 1;
  __REG32 RFF               : 1;
  __REG32 RFE               : 1;
  __REG32 TFF               : 1;
  __REG32 TFE               : 1;
  __REG32                   :20;
} __i2c_sts_bits;

/* I2C Control Register */
typedef struct{
  __REG32 TDIE              : 1;
  __REG32                   : 1;
  __REG32 NAIE              : 1;
  __REG32 DRMIE             : 1;
  __REG32                   : 1;
  __REG32 DAIE              : 1;
  __REG32 RFDAIE            : 1;
  __REG32 TFFIE             : 1;
  __REG32 RESET             : 1;
  __REG32                   :23;
} __i2c_ctrl_bits;

/* I2C Clock Divider High */
typedef struct{
  __REG32 CLK_DIV_HI        :10;
  __REG32                   :22;
} __i2c_clk_hi_bits;

/* I2C Clock Divider Low */
typedef struct{
  __REG32 CLK_DIV_LO        :10;
  __REG32                   :22;
} __i2c_clk_lo_bits;

/* Keypad State Machine Current State Register */
typedef struct{
  __REG8  STATE             : 2;
  __REG8                    : 6;
} __ks_state_cond_bits;

/* Keypad State Machine Current State Register */
typedef struct{
  __REG8  KIRQN             : 1;
  __REG8                    : 7;
} __ks_irq_bits;

/* Keypad Scan Clock Control Register */
typedef struct{
  __REG8  ScanOnce          : 1;
  __REG8  Clk32             : 1;
  __REG8                    : 6;
} __ks_fast_tst_bits;

/* Keypad Matrix Dimension Select Register */
typedef struct{
  __REG8  MX_DIM            : 4;
  __REG8                    : 4;
} __ks_matrix_dim_bits;

/* High Speed Timer Interrupt Status Register */
typedef struct{
  __REG32 MATCH0_INT        : 1;
  __REG32 MATCH1_INT        : 1;
  __REG32 MATCH2_INT        : 1;
  __REG32                   : 1;
  __REG32 GPI_06            : 1;
  __REG32 RTC_TICK          : 1;
  __REG32                   :26;
} __hstim_int_bits;

/* High Speed Timer Control Register */
typedef struct{
  __REG32 COUNT_ENAB        : 1;
  __REG32 RESET_COUNT       : 1;
  __REG32 PAUSE_EN          : 1;
  __REG32                   :29;
} __hstim_ctrl_bits;

/* High Speed Timer Match Control Register */
typedef struct{
  __REG32 MR0_INT           : 1;
  __REG32 RESET_COUNT0      : 1;
  __REG32 STOP_COUNT0       : 1;
  __REG32 MR1_INT           : 1;
  __REG32 RESET_COUNT1      : 1;
  __REG32 STOP_COUNT1       : 1;
  __REG32 MR2_INT           : 1;
  __REG32 RESET_COUNT2      : 1;
  __REG32 STOP_COUNT2       : 1;
  __REG32                   :23;
} __hstim_mctrl_bits;

/* High Speed Timer Capture Control Register */
typedef struct{
  __REG32 RISING_EDGE       : 1;
  __REG32 FALLING_EDGE      : 1;
  __REG32 HSTIM_INT         : 1;
  __REG32 RTC_TICK_RISE     : 1;
  __REG32 RTC_TICK_FALL     : 1;
  __REG32 RTC_TICK_EVENT    : 1;
  __REG32                   :26;
} __hstim_ccr_bits;

/* MilliSecond Timer Interrupt Status Register */
typedef struct{
  __REG32 MATCH0_INT1       : 1;
  __REG32 MATCH0_INT2       : 1;
  __REG32                   :30;
} __mstim_int_bits;

/* MilliSecond Timer Control Register */
typedef struct{
  __REG32 COUNT_ENAB        : 1;
  __REG32 RESET_COUNT       : 1;
  __REG32 PAUSE_EN          : 1;
  __REG32                   :29;
} __mstim_ctrl_bits;

/* MilliSecond Timer Match Control Register */
typedef struct{
  __REG32 MR0_INT           : 1;
  __REG32 RESET_COUNT0      : 1;
  __REG32 STOP_COUNT0       : 1;
  __REG32 MR1_INT           : 1;
  __REG32 RESET_COUNT1      : 1;
  __REG32 STOP_COUNT1       : 1;
  __REG32                   :26;
} __mstim_mctrl_bits;

/* PWM1 Control Register */
typedef struct{
  __REG32 PWM1_DUTY         : 8;
  __REG32 PWM1_RELOADV      : 8;
  __REG32                   :14;
  __REG32 PWM1_PIN_LEVEL    : 1;
  __REG32 PWM1_EN           : 1;
} __pwm1_ctrl_bits;

/* PWM2 Control Register */
typedef struct{
  __REG32 PWM2_DUTY         : 8;
  __REG32 PWM2_RELOADV      : 8;
  __REG32                   :13;
  __REG32 PWM2_INT          : 1;
  __REG32 PWM2_PIN_LEVEL    : 1;
  __REG32 PWM2_EN           : 1;
} __pwm2_ctrl_bits;

/* RTC Control Register */
typedef struct{
  __REG32 MATCH0_INTE       : 1;
  __REG32 MATCH1_INTE       : 1;
  __REG32 MATCH0_ONSW       : 1;
  __REG32 MATCH1_ONSW       : 1;
  __REG32 RESET             : 1;
  __REG32                   : 1;
  __REG32 CLK_DIS           : 1;
  __REG32 FORCE_ONSW        : 1;
  __REG32                   : 2;
  __REG32 RTC_CLK           : 1;
  __REG32                   :21;
} __rtc_ctrl_bits;

/* PWM2 Control Register */
typedef struct{
  __REG32 MATCH0_INT        : 1;
  __REG32 MATCH1_INT        : 1;
  __REG32 ONSW_STATUS       : 1;
  __REG32                   :29;
} __rtc_intstat_bits;

/* Watchdog Timer Interrupt Status Register */
typedef struct{
  __REG32 MATCH_INT         : 1;
  __REG32                   :31;
} __wdtim_int_bits;

/* Watchdog Timer Control Register */
typedef struct{
  __REG32 COUNT_ENAB        : 1;
  __REG32 RESET_COUNT       : 1;
  __REG32 PAUSE_EN          : 1;
  __REG32                   :29;
} __wdtim_ctrl_bits;

/* Watchdog Timer Match Control Register */
typedef struct{
  __REG32 MR0_INT           : 1;
  __REG32 RESET_COUNT0      : 1;
  __REG32 STOP_COUNT0       : 1;
  __REG32 M_RES1            : 1;
  __REG32 M_RES2            : 1;
  __REG32 RESFRC1           : 1;
  __REG32 RESFRC2           : 1;
  __REG32                   :25;
} __wdtim_mctrl_bits;

/* Watchdog Timer External Match Control Register */
typedef struct{
  __REG32 EXT_MATCH0        : 1;
  __REG32                   : 3;
  __REG32 MATCH_CTRL        : 2;
  __REG32                   :26;
} __wdtim_emr_bits;

/* A/D Status Register */
typedef struct{
  __REG32                   : 4;
  __REG32 ADC_STAT          : 3;
  __REG32                   :25;
} __adstat_bits;

/* A/D Select Register */
typedef struct{
  __REG32                   : 4;
  __REG32 AD_IN             : 2;
  __REG32 AD_REF_P          : 2;
  __REG32 AD_REF_N          : 2;
  __REG32                   :22;
} __adsel_bits;

/* A/D Control Register */
typedef struct{
  __REG32                   : 1;
  __REG32 AD_STROBE         : 1;
  __REG32 AD_PDN_CTRL       : 1;
  __REG32                   : 4;
  __REG32 AD_ACC            : 3;
  __REG32                   :22;
} __adcon_bits;

/* A/D Data Register */
typedef struct{
  __REG32 ADC_VALUE         :10;
  __REG32                   :22;
} __addat_bits;

/* DMA Interrupt Status Register
   DMA Interrupt Terminal Count Request Status Register
   DMA Interrupt Terminal Count Request Clear Register
   DMA Interrupt Error Status Register
   DMA Interrupt Error Clear Register
   DMA Raw Interrupt Terminal Count Status Register
   DMA Raw Error Interrupt Status Register
   DMA Enabled Channel Register */
typedef struct{
  __REG32 DMA_CH0           : 1;
  __REG32 DMA_CH1           : 1;
  __REG32 DMA_CH2           : 1;
  __REG32 DMA_CH3           : 1;
  __REG32 DMA_CH4           : 1;
  __REG32 DMA_CH5           : 1;
  __REG32 DMA_CH6           : 1;
  __REG32 DMA_CH7           : 1;
  __REG32                   :24;
} __DMACIntStat_bits;

/* DMA Software Burst Request Register
   DMA Software Single Request Register
   DMA Software Last Burst Request Register
   DMA Software Last Single Request Register
   DMA Synchronization Register */
typedef struct{
  __REG32 DMA_LINE0         : 1;
  __REG32 DMA_LINE1         : 1;
  __REG32 DMA_LINE2         : 1;
  __REG32 DMA_LINE3         : 1;
  __REG32 DMA_LINE4         : 1;
  __REG32 DMA_LINE5         : 1;
  __REG32 DMA_LINE6         : 1;
  __REG32 DMA_LINE7         : 1;
  __REG32 DMA_LINE8         : 1;
  __REG32 DMA_LINE9         : 1;
  __REG32 DMA_LINE10        : 1;
  __REG32 DMA_LINE11        : 1;
  __REG32 DMA_LINE12        : 1;
  __REG32 DMA_LINE13        : 1;
  __REG32 DMA_LINE14        : 1;
  __REG32 DMA_LINE15        : 1;
  __REG32                   :16;
} __DMACSoftBReq_bits;

/* DMA Software Burst Request Register
   DMA Software Single Request Register
   DMA Software Last Burst Request Register
   DMA Software Last Single Request Register
   DMA Synchronization Register */
typedef struct{
  __REG32 E                 : 1;
  __REG32 M0                : 1;
  __REG32 M1                : 1;
  __REG32                   :29;
} __DMACConfig_bits;

/* DMA Software Burst Request Register */
typedef struct{
  __REG32 LM                : 1;
  __REG32                   : 1;
  __REG32 LLI               :30;
} __dma_lli_bits;

/* DMA Software Burst Request Register */
typedef struct{
  __REG32 TransferSize      :12;
  __REG32 SBSize            : 3;
  __REG32 DBSize            : 3;
  __REG32 SWidth            : 3;
  __REG32 DWidth            : 3;
  __REG32 S                 : 1;
  __REG32 D                 : 1;
  __REG32 SI                : 1;
  __REG32 DI                : 1;
  __REG32 Prot1             : 1;
  __REG32 Prot2             : 1;
  __REG32 Prot3             : 1;
  __REG32 I                 : 1;
} __dma_ctrl_bits;

/* DMA Software Burst Request Register */
typedef struct{
  __REG32 E                 : 1;
  __REG32 SrcPeripheral     : 5;
  __REG32 DestPeripheral    : 5;
  __REG32 FlowCntrl         : 3;
  __REG32 IE                : 1;
  __REG32 ITC               : 1;
  __REG32 L                 : 1;
  __REG32 A                 : 1;
  __REG32 H                 : 1;
  __REG32                   :13;
} __dma_cfg_bits;

/* DMA Peripheral ID Register 1 */
typedef struct{
  __REG8  PartNumber1       : 4;
  __REG8  Designer0         : 4;
} __dma_id1_bits;

/* DMA Peripheral ID Register 2 */
typedef struct{
  __REG8  Designer1         : 4;
  __REG8  Revision          : 4;
} __dma_id2_bits;

/* DMA Peripheral ID Register 3 */
typedef struct{
  __REG8  CH_NUMB           : 3;
  __REG8  AHB_NUMB          : 1;
  __REG8  AHB_WIDTH         : 3;
  __REG8  DMA_32            : 1;
} __dma_id3_bits;

#endif    /* __IAR_SYSTEMS_ICC__ */

/* Declarations common to compiler and assembler **************************/

/***************************************************************************
 **
 ** System control block
 **
 ***************************************************************************/
__IO_REG32_BIT(BOOT_MAP,              0x40004014,__READ_WRITE,__boot_map_bits);
__IO_REG32_BIT(PWR_CTRL,              0x40004044,__READ_WRITE,__pwr_ctrl_bits);
__IO_REG32_BIT(OSC_CTRL,              0x4000404C,__READ_WRITE,__osc_ctrl_bits);
__IO_REG32_BIT(SYSCLK_CTRL,           0x40004050,__READ_WRITE,__sysclk_ctrl_bits);
__IO_REG32_BIT(PLL397_CTRL,           0x40004048,__READ_WRITE,__pll397_ctrl_bits);
__IO_REG32_BIT(HCLKPLL_CTRL,          0x40004058,__READ_WRITE,__hclkpll_ctrl_bits);
__IO_REG32_BIT(HCLKDIV_CTRL,          0x40004040,__READ_WRITE,__hclkdiv_ctrl_bits);
__IO_REG32_BIT(TEST_CLK,              0x400040A4,__READ_WRITE,__test_clk_bits);
__IO_REG32_BIT(AUTOCLK_CTRL,          0x400040EC,__READ_WRITE,__autoclk_ctrl_bits);
__IO_REG32_BIT(START_ER_INT,          0x40004020,__READ_WRITE,__start_er_int_bits);
__IO_REG32_BIT(START_ER_PIN,          0x40004030,__READ_WRITE,__start_er_pin_bits);
__IO_REG32_BIT(START_RSR_INT,         0x40004024,__READ_WRITE,__start_er_int_bits);
__IO_REG32_BIT(START_RSR_PIN,         0x40004034,__READ_WRITE,__start_er_pin_bits);
__IO_REG32_BIT(START_SR_INT,          0x40004028,__READ      ,__start_er_int_bits);
__IO_REG32_BIT(START_SR_PIN,          0x40004038,__READ      ,__start_er_pin_bits);
__IO_REG32_BIT(START_APR_INT,         0x4000402C,__READ_WRITE,__start_er_int_bits);
__IO_REG32_BIT(START_APR_PIN,         0x4000403C,__READ_WRITE,__start_er_pin_bits);
__IO_REG32_BIT(DMACLK_CTRL,           0x400040E8,__READ_WRITE,__dmaclk_ctrl_bits);
__IO_REG32_BIT(UARTCLK_CTRL,          0x400040E4,__READ_WRITE,__uartclk_ctrl_bits);
__IO_REG32_BIT(USB_CTRL,              0x40004064,__READ_WRITE,__usb_ctrl_bits);
__IO_REG32_BIT(MS_CTRL,               0x40004080,__READ_WRITE,__ms_ctrl_bits);
__IO_REG32_BIT(I2CCLK_CTRL,           0x400040AC,__READ_WRITE,__i2cclk_ctrl_bits);
__IO_REG32_BIT(KEYCLK_CTRL,           0x400040B0,__READ_WRITE,__keyclk_ctrl_bits);
__IO_REG32_BIT(ADCLK_CTRL,            0x400040B4,__READ_WRITE,__adclk_ctrl_bits);
__IO_REG32_BIT(PWMCLK_CTRL,           0x400040B8,__READ_WRITE,__pwmclk_ctrl_bits);
__IO_REG32_BIT(TIMCLK_CTRL,           0x400040BC,__READ_WRITE,__timclk_ctrl_bits);
__IO_REG32_BIT(SPI_CTRL,              0x400040C4,__READ_WRITE,__spi_ctrl_bits);
__IO_REG32_BIT(FLASHCLK_CTRL,         0x400040C8,__READ_WRITE,__flashclk_ctrl_bits);

/***************************************************************************
 **
 ** SDRAM MEMORY CONTROLLER
 **
 ***************************************************************************/
__IO_REG32_BIT(SDRAMCLK_CTRL,         0x40004068,__READ_WRITE,__sdramclk_ctrl_bits);
__IO_REG32_BIT(MPMCControl,           0x31080000,__READ_WRITE,__mpmc_ctrl_bits);
__IO_REG32_BIT(MPMCStatus,            0x31080004,__READ      ,__mpmc_status_bits);
__IO_REG32_BIT(MPMCConfig,            0x31080008,__READ_WRITE,__mpmc_cfg_bits);
__IO_REG32_BIT(MPMCDynamicControl,    0x31080020,__READ_WRITE,__mpmcd_ctrl_bits);
__IO_REG32_BIT(MPMCDynamicRefresh,    0x31080024,__READ_WRITE,__mpmcd_refresh_bits);
__IO_REG32_BIT(MPMCDynamicReadConfig, 0x31080028,__READ_WRITE,__mpmcd_read_