📄 iolpc3100.h
字号:
/***************************************************************************
**
** This file defines the Special Function Registers for
** Philips LPC3100
**
** Used with ARM IAR C/C++ Compiler and Assembler.
**
** (c) Copyright IAR Systems 2006
**
** $Revision: 1.0 $
**
** Note:
***************************************************************************/
#ifndef __IOLPC3100_H
#define __IOLPC3100_H
#if (((__TID__ >> 8) & 0x7F) != 0x4F) /* 0x4F = 79 dec */
#error This file should only be compiled by ARM IAR compiler and assembler
#endif
#include "io_macros.h"
/***************************************************************************
***************************************************************************
**
** LPC3100 SPECIAL FUNCTION REGISTERS
**
***************************************************************************
***************************************************************************
***************************************************************************/
/* C-compiler specific declarations ***************************************/
#ifdef __IAR_SYSTEMS_ICC__
/* Boot Map Control Register */
typedef struct{
__REG32 MAP : 1;
__REG32 :31;
} __boot_map_bits;
/* Power Control Register Register */
typedef struct{
__REG32 STOP_MODE : 1;
__REG32 HIGHCORE_SEL : 1;
__REG32 RUN_MODE : 1;
__REG32 SYSCLKEN_SEL : 1;
__REG32 SYSCLKEN_OUT : 1;
__REG32 HIGHCORE_OUT : 1;
__REG32 USB_HCLK : 1;
__REG32 SDRAM_AESR : 1;
__REG32 MPMCSREFREQ_UPDATE : 1;
__REG32 MPMCSREFREQ_VALUE : 1;
__REG32 HCKL_FORCE : 1;
__REG32 :21;
} __pwr_ctrl_bits;
/* Main Oscillator Control Register */
typedef struct{
__REG32 ENABLE : 1;
__REG32 TEST : 1;
__REG32 CAP_SEL : 7;
__REG32 :23;
} __osc_ctrl_bits;
/* SYSCLK Control Register */
typedef struct{
__REG32 SYSCLK_MUX : 1;
__REG32 SYSCLK_SEL : 1;
__REG32 SYSCLK_SWITCH_DLY :10;
__REG32 :20;
} __sysclk_ctrl_bits;
/* PLL397 Control Register */
typedef struct{
__REG32 PLL_LOCK : 1;
__REG32 PLL397_STATUS : 1;
__REG32 : 4;
__REG32 PLL397_BIAS : 3;
__REG32 PLL397_BYPASS : 1;
__REG32 PLL_MSLOCK : 1;
__REG32 :21;
} __pll397_ctrl_bits;
/* HCLK PLL Control Register */
typedef struct{
__REG32 PLL_LOCK : 1;
__REG32 M : 8;
__REG32 N : 2;
__REG32 P : 2;
__REG32 FEEDBACK : 1;
__REG32 DIRECT : 1;
__REG32 BYPASS : 1;
__REG32 POWER_DOWN : 1;
__REG32 :15;
} __hclkpll_ctrl_bits;
/* HCLK Divider Control Register */
typedef struct{
__REG32 HCLK : 2;
__REG32 PERIPH_CLK : 5;
__REG32 DDRAM_CLK : 2;
__REG32 :23;
} __hclkdiv_ctrl_bits;
/* Test Clock Selection Register */
typedef struct{
__REG32 TST_CLK2 : 1;
__REG32 TST_CLK2_SEL: 3;
__REG32 TST_CLK1 : 1;
__REG32 TST_CLK1_SEL: 2;
__REG32 :25;
} __test_clk_bits;
/* Autoclock Control Register */
typedef struct{
__REG32 IROM : 1;
__REG32 IRAM : 1;
__REG32 : 4;
__REG32 USB_SLAVE : 1;
__REG32 :25;
} __autoclk_ctrl_bits;
/* Start Enable Register for Internal Sources */
typedef struct{
__REG32 GPIO_00 : 1;
__REG32 GPIO_01 : 1;
__REG32 GPIO_02 : 1;
__REG32 GPIO_03 : 1;
__REG32 GPIO_04 : 1;
__REG32 GPIO_05 : 1;
__REG32 :10;
__REG32 KEY_IRQ : 1;
__REG32 : 2;
__REG32 USB_OTG_ATX_INT_N : 1;
__REG32 USB_OTG_TIMER_INT : 1;
__REG32 USB_I2C_INT : 1;
__REG32 USB_INT : 1;
__REG32 USB_NEED_CLK : 1;
__REG32 RTC_INT : 1;
__REG32 MSTIMER_INT : 1;
__REG32 USB_AHB_NEED_CLK : 1;
__REG32 : 4;
__REG32 AD_IRQ : 1;
} __start_er_int_bits;
/* Start Enable Register for Pin Sources */
typedef struct{
__REG32 : 3;
__REG32 GPI_08 : 1;
__REG32 GPI_09 : 1;
__REG32 GPI_10 : 1;
__REG32 SPI2_DATIN : 1;
__REG32 GPI_07 : 1;
__REG32 SPI1_DATIN : 1;
__REG32 SYSCLKEN_PIN : 1;
__REG32 GPI_00 : 1;
__REG32 GPI_01 : 1;
__REG32 GPI_02 : 1;
__REG32 GPI_03 : 1;
__REG32 GPI_04 : 1;
__REG32 GPI_05 : 1;
__REG32 GPI_06 : 1;
__REG32 MSDIO_START : 1;
__REG32 SDIO_INT_N : 1;
__REG32 : 2;
__REG32 U1_RX : 1;
__REG32 U2_RX : 1;
__REG32 U2_HCTS : 1;
__REG32 U3_RX : 1;
__REG32 GPI_11 : 1;
__REG32 U5_RX : 1;
__REG32 : 1;
__REG32 U6_IRRX : 1;
__REG32 : 1;
__REG32 U7_HCTS : 1;
__REG32 U7_RX : 1;
} __start_er_pin_bits;
/* DMA Clock Control Register */
typedef struct{
__REG32 DMA_CLK_ENA : 1;
__REG32 :31;
} __dmaclk_ctrl_bits;
/* UART Clock Control Register */
typedef struct{
__REG32 UART3_CLK_ENA : 1;
__REG32 UART4_CLK_ENA : 1;
__REG32 UART5_CLK_ENA : 1;
__REG32 UART6_CLK_ENA : 1;
__REG32 :28;
} __uartclk_ctrl_bits;
/* USB Control Register */
typedef struct{
__REG32 PLL_LOCK : 1;
__REG32 M : 8;
__REG32 N : 2;
__REG32 P : 2;
__REG32 FEEDBACK : 1;
__REG32 DIRECT : 1;
__REG32 BYPASS : 1;
__REG32 POWER_DOWN : 1;
__REG32 USB_Clken1 : 1;
__REG32 USB_Clken2 : 1;
__REG32 PAD_CTRL : 2;
__REG32 HOST_NEED_CLK_ENA : 1;
__REG32 DEV_NEED_CLK_ENA : 1;
__REG32 I2C_ENA : 1;
__REG32 SLAVE_HCLK_CTRL : 1;
__REG32 : 7;
} __usb_ctrl_bits;
/* Memory Card Control Register */
typedef struct{
__REG32 MSSDCLK_SEL : 4;
__REG32 : 1;
__REG32 CLK_ENA : 1;
__REG32 MSSDIO0_PAD_CTRL : 1;
__REG32 MSSDIO1_PAD_CTRL : 1;
__REG32 MSSDIO2_3_PAD_CTRL: 1;
__REG32 PULL_UP_ENA : 1;
__REG32 :22;
} __ms_ctrl_bits;
/* I2C Clock Control Register */
typedef struct{
__REG32 I2C1_CLK_ENA : 1;
__REG32 I2C2_CLK_ENA : 1;
__REG32 I2C1_DRV_MODE : 1;
__REG32 I2C2_DRV_MODE : 1;
__REG32 USB_I2C_DRV_MODE : 1;
__REG32 :27;
} __i2cclk_ctrl_bits;
/* Keyboard Scan Clock Control Register */
typedef struct{
__REG32 CLK_ENA : 1;
__REG32 :31;
} __keyclk_ctrl_bits;
/* ADC Clock Control Register */
typedef struct{
__REG32 CLK_ENA : 1;
__REG32 :31;
} __adclk_ctrl_bits;
/* PWM Clock Control Register */
typedef struct{
__REG32 PWM1_CLK_ENA : 1;
__REG32 PWM1_CLK_SEL : 1;
__REG32 PWM2_CLK_ENA : 1;
__REG32 PWM2_CLK_SEL : 1;
__REG32 PWM1_FREQ : 4;
__REG32 PWM2_FREQ : 4;
__REG32 :20;
} __pwmclk_ctrl_bits;
/* Timer Clock Control Regis */
typedef struct{
__REG32 WDT_CLK_ENA : 1;
__REG32 HST_CLK_ENA : 1;
__REG32 :30;
} __timclk_ctrl_bits;
/* SPI Block Control Register */
typedef struct{
__REG32 SPI1_CLK_ENA : 1;
__REG32 SPI1_PIN_SEL : 1;
__REG32 SPI1_CLK_OUT : 1;
__REG32 SPI1_DATIO : 1;
__REG32 SPI2_CLK_ENA : 1;
__REG32 SPI2_PIN_SEL : 1;
__REG32 SPI2_CLK_OUT : 1;
__REG32 SPI2_DATIO : 1;
__REG32 :24;
} __spi_ctrl_bits;
/* NAND Flash Clock Control Register */
typedef struct{
__REG32 SLC_NAND_ENA : 1;
__REG32 MLC_NAND_ENA : 1;
__REG32 SLC_MLC_SEL : 1;
__REG32 DMA_NAND_INT_ENA : 1;
__REG32 DMA_NAND_RnB_ENA : 1;
__REG32 INT_SEL : 1;
__REG32 :26;
} __flashclk_ctrl_bits;
/* SDRAM Clock Control Register */
typedef struct{
__REG32 CLK_DIS : 1;
__REG32 DDR_SEL : 1;
__REG32 DDR_DQSIN_DELAY : 4;
__REG32 RTC_TICK_EN : 1;
__REG32 SW_DDR_CAL : 1;
__REG32 CAL_DELAY : 1;
__REG32 SENS_FACTOR : 3;
__REG32 DLY_ADD_STATUS : 1;
__REG32 HCLKDELAY_DELAY : 5;
__REG32 SW_DDR_RESET : 1;
__REG32 SDRAM_PIN_SPEED1 : 1;
__REG32 SDRAM_PIN_SPEED2 : 1;
__REG32 SDRAM_PIN_SPEED3 : 1;
__REG32 :10;
} __sdramclk_ctrl_bits;
/* SDRAM Controller Control Register */
typedef struct{
__REG32 E : 1;
__REG32 : 1;
__REG32 L : 1;
__REG32 :29;
} __mpmc_ctrl_bits;
/* SDRAM Controller Status Register */
typedef struct{
__REG32 B : 1;
__REG32 : 1;
__REG32 SA : 1;
__REG32 :29;
} __mpmc_status_bits;
/* SDRAM Controller Configuration Register */
typedef struct{
__REG32 N : 1;
__REG32 :31;
} __mpmc_cfg_bits;
/* Dynamic Memory Control Register */
typedef struct{
__REG32 CE : 1;
__REG32 CS : 1;
__REG32 SR : 1;
__REG32 SRMCC : 1;
__REG32 IMCC : 1;
__REG32 MMC : 1;
__REG32 : 1;
__REG32 I : 2;
__REG32 : 4;
__REG32 DP : 1;
__REG32 :18;
} __mpmcd_ctrl_bits;
/* Dynamic Memory Refresh Timer Register */
typedef struct{
__REG32 REFRESH :11;
__REG32 :21;
} __mpmcd_refresh_bits;
/* Dynamic Memory Read Configuration Register */
typedef struct{
__REG32 SRD : 2;
__REG32 : 2;
__REG32 SRP : 1;
__REG32 : 3;
__REG32 DRD : 2;
__REG32 : 2;
__REG32 DRP : 1;
__REG32 :19;
} __mpmcd_read_cfg_bits;
/* Dynamic Memory Precharge Command Period Register */
typedef struct{
__REG32 tRP : 4;
__REG32 :28;
} __mpmcd_trp_bits;
/* Dynamic Memory Active to Precharge Command Period Register */
typedef struct{
__REG32 tRAS : 4;
__REG32 :28;
} __mpmcd_tras_bits;
/* Dynamic Memory Self-refresh Exit Time Register */
typedef struct{
__REG32 tSREX : 7;
__REG32 :25;
} __mpmcd_tsrex_bits;
/* Dynamic Memory Write Recovery Time Register */
typedef struct{
__REG32 tWR : 4;
__REG32 :28;
} __mpmcd_twr_bits;
/* Dynamic Memory Active To Active Command Period Register */
typedef struct{
__REG32 tRC : 5;
__REG32 :27;
} __mpmcd_trc_bits;
/* Dynamic Memory Auto-refresh Period Register */
typedef struct{
__REG32 tRFC : 5;
__REG32 :27;
} __mpmcd_trfc_bits;
/* Dynamic Memory Exit Self-refresh Register */
typedef struct{
__REG32 tXSR : 8;
__REG32 :24;
} __mpmcd_txsr_bits;
/* Dynamic Memory Active Bank A to Active Bank B Time Register */
typedef struct{
__REG32 tRRD : 4;
__REG32 :28;
} __mpmcd_trrd_bits;
/* Dynamic Memory Load Mode Register To Active Command Time */
typedef struct{
__REG32 tMRD : 4;
__REG32 :28;
} __mpmcd_tmrd_bits;
/* Dynamic Memory Last Data In to Read Command Time */
typedef struct{
__REG32 tCDLR : 4;
__REG32 :28;
} __mpmcd_tcdlr_bits;
/* Dynamic Memory Configuration Register */
typedef struct{
__REG32 MD : 3;
__REG32 : 4;
__REG32 AM : 8;
__REG32 : 5;
__REG32 P : 1;
__REG32 :11;
} __mpmcd_cfg_bits;
/* Dynamic Memory RAS & CAS Delay Register */
typedef struct{
__REG32 RAS : 4;
__REG32 : 3;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -