bsp.c.2006-04-14.12-44-15.4375

uCOSII 在LPC3180上的移植代码

* Description: This function reads CPU registers to determine the CPU clock frequency of the chip.
*
*              Where ARMCPUCLK = FCLKOUT = (M * FCLKIN) / N
*                    and FCLKIN is defined by CPU_OSC_FREQ in BSP.H
*                    and M, N are PLL configuration settings.
*
* Returns    : The CPU frequency (HZ), assuming the PLL is on in Direct Mode, and the CPU is running
*              in 'Normal Run Mode'
*********************************************************************************************************
*/

INT32U  BSP_CPU_ClkFrq (void)
{

    INT32U  PLLCtl;
    INT32U  PLL_m;
    INT32U  PLL_n;
    FP32    cpu_clk_frq;


    PLLCtl            =   HCLKPLL_CTRL;                                     /* Get the value of the PLL control register            */
    PLLCtl            = ((PLLCtl >> 14) & 0x03);                            /* Isolate bits [15:14], shift over to positions [1:0]  */

                                                                            /* If the PLL in direct Mode (bit 15 = 0, bit 14 = 1)   */
    if ((PLLCtl  == 0x01) && ((PWR_CTRL & 0x02) == 0x02)) {                 /* and the CPU is running in 'Normal Run Mode'          */
        PLL_m         =  ((HCLKPLL_CTRL >> 1) & 0xFF) + 1;                  /* Determine the PLL value for M                        */
        PLL_n         =  ((HCLKPLL_CTRL >> 9) & 0x03) + 1;                  /* Determine the PLL value for N                        */
        cpu_clk_frq   =  ((PLL_m * CPU_OSC_FREQ) / PLL_n);                  /* Calculate the operating frequency                    */
    } else {
        cpu_clk_frq   =    0;                                               /* If we are not in Direct Mode, return 0               */
    }

    return ((INT32U)cpu_clk_frq);                                           /* Return the operating frequency                       */
}

/*
*********************************************************************************************************
*                                   Get the Peripheral Clock Frequency
*
* Description: This function determines the peripheral clock frequency of the chip.
*              It relies on the existance of BSP_CPU_ClkFrq() which assumes the chip is in
*              'Normal Run Mode', and that the PLL is running under 'Direct Mode'.
*              If these conditions are not met, this function will return 0 since
*              BSP_CPU_ClkFrq() will return 0.
*********************************************************************************************************
*/

INT32U  BSP_ClkFrqPeripheral (void)
{
    INT32U  cpu_frq;
    INT32U  periphClkDiv;
    FP32    periphClkFrq;


    cpu_frq          =    BSP_CPU_ClkFrq();                                 /* Get the FCLKOUT (HCLK PLL) output frequency               */
    periphClkDiv     =  ((HCLKDIV_CTRL >> 2) & 0x1F) + 1;                   /* Read the Peripheral Clock Divider Value                   */

    periphClkFrq     =   (cpu_frq / periphClkDiv);                          /* Calculate the Peripheral Clock Frequency in hz            */

    return ((INT32U)periphClkFrq);                                          /* Return the Peripheral Clock Frequency                     */
}

/*
*********************************************************************************************************
*                                   Get the HCLK Frequency
*
* Description: This function determines the peripheral clock frequency of the chip.
*              It relies on the existance of BSP_CPU_ClkFrq() which assumes the chip is in
*              'Normal Run Mode', and that the PLL is running under 'Direct Mode'.
*              If these conditions are not met, this function will return 0 since
*              BSP_CPU_ClkFrq() will return 0.
*
* Note       : HCLK is the system BUS clock source
*********************************************************************************************************
*/

INT32U  BSP_ClkFrqHCLK (void)
{
    INT32U  cpu_frq;
    INT32U  HCLKDiv;
    FP32    HCLKFrq;


    cpu_frq          =    BSP_CPU_ClkFrq();                                 /* Get the FCLKOUT (HCLK PLL) output frequency               */
    HCLKDiv           =   (HCLKDIV_CTRL & 0x03) + 1;                        /* Read the HCLK Divider Value                               */

    if (HCLKDiv == 0) {                                                     /* If the divider  value = 0, then we have a divider of 1    */
        HCLKDiv       =   1;
    } else {
         HCLKDiv     *=   2;                                                /* Calculate the correct divider from the register value     */
    }

    HCLKFrq           =   (cpu_frq / HCLKDiv);                              /* Calculate the HCLK Frequency in hz                        */

    return ((INT32U)HCLKFrq);                                               /* Return the Peripheral Clock Frequency                     */
}

/*
*********************************************************************************************************
*                                     BSP INTERRUPT ENABLE
*
* Description : This function enables and configures interrupt handlers for the 64 possible interrupts
*
* Arguments   : IntCont -  Specify which sub controller block to enable the interrupt on. Possible values: 0, 1, 2.
*                          where sub interrupt controller 0 is the main interrupt enable register
*               IntNum  -  Specify which sub controller interrupt number to enable. Possible values: 0-31
*               IntPol  -  Specify the Interrupt Polarity
*                              0 = Active low level or falling edge
*                              1 = Active high level or rising edge
*               IntAct  -  Specify whether an interrupt source is either level or edge sensitive
*                              0 = Interrupt is level sensitive
*                              1 = Interrupt is edge sensitive
*               Handler -  Specify a function pointer to the associated interrupt handler
*
* Notes       : 1) This function is only intended to enable Normal Interrupts, not FIQ's
*               2) Edge Sensitive interrupts must be cleared not only at the source but in the
*                  Raw Interrupt Status Register as well.
*               3) Setting polarity or edge sensitivity for any of the SUB INTERRUPT CONTROLLERS is
*                  possible, but only for the entire sub controller and all attached devices as a whole.
*                  If this function is called twice, once enabling level sensitivity for a sub1 device,
*                  and a second time enabling edge sensitivity for a different device on the same sub
*                  controller, then level sensitivity will be cancelled by the settings specified in
*                  the second call to BSP_IntEn(SUBn, x, x, x, x).
*********************************************************************************************************
*/

void  BSP_IntEn (INT8U IntCont, INT8U IntNum, INT8U IntPol, INT8U IntAct, PFNCT pfnct)
{
    if ((IntNum < 32) && (pfnct != (PFNCT)0)) {                             /* If the IntNum and ISR Handler pointer are valid      */
        switch (IntCont) {
            case 0:
                 if (IntPol == BSP_INT_LOW_LEVEL) {
                     MIC_APR  &= ~(1 << IntNum);                            /* Set the interrupt number as low level / falling edge */
                 } else {
                     MIC_APR  |=  (1 << IntNum);                            /* Set the interrupt number as high level / rising edge */
                 }

                 if (IntAct == BSP_INT_LEVEL_SENSITIVE) {
                     MIC_ATR  &= ~(1 << IntNum);                            /* Set the interrupt number as level sensitive          */
                 } else {
                     MIC_ATR  |=  (1 << IntNum);                            /* Set the interrupt number as edge sensitive           */
                 }

                 BSP_IntVectTbl[BSP_MAIN_INT_CTL][IntNum] = pfnct;          /* Save the ISR Handler function pointer                */
                 MIC_ER  |= (1 << IntNum);                                  /* Enable the IntNum on the main interrupt controller   */
                 break;

            case 1:
                 if (IntPol == BSP_INT_LOW_LEVEL) {
                     MIC_APR  &= ~(1 << 0);                                 /* Set the interrupt number as low level / falling edge */
                 } else {
                     MIC_APR  |=  (1 << 0);                                 /* Set the interrupt number as high level / rising edge */
                 }

                 if (IntAct == BSP_INT_LEVEL_SENSITIVE) {
                     MIC_ATR  &= ~(1 << 0);                                 /* Set the interrupt number as level sensitive          */
                 } else {
                     MIC_ATR  |=  (1 << 0);                                 /* Set the interrupt number as edge sensitive           */
                 }

                 BSP_IntVectTbl[BSP_SUB1_INT_CTL][IntNum] = pfnct;          /* Save the ISR Handler function pointer                */
                 MIC_ER  |= (1 << 0);                                       /* Ensure that Sub1IRQn (sub interrupts 1) are enabled  */
                 SIC1_ER |= (1 << IntNum);                                  /* Enable the IntNum on the sub interrupt controller 1  */
                 break;

            case 2:
                 if (IntPol == BSP_INT_LOW_LEVEL) {
                     MIC_APR  &= ~(1 << 1);                                 /* Set the interrupt number as low level / falling edge */
                 } else {
                     MIC_APR  |=  (1 << 1);                                 /* Set the interrupt number as high level / rising edge */
                 }

                 if (IntAct == BSP_INT_LEVEL_SENSITIVE) {
                     MIC_ATR  &= ~(1 << 1);                                 /* Set the interrupt number as level sensitive          */
                 } else {
                     MIC_ATR  |=  (1 << 1);                                 /* Set the interrupt number as edge sensitive           */
                 }

                 BSP_IntVectTbl[BSP_SUB2_INT_CTL][IntNum] = pfnct;          /* Save the ISR Handler function pointer                */
                 MIC_ER  |= (1 << 1);                                       /* Ensure that Sub2IRQn (sub interrupts 2) are enabled  */
                 SIC2_ER |= (1 << IntNum);                                  /* Enable the IntNum on the sub interrupt controller 2  */
                 break;
        }
    }
}

/*
*********************************************************************************************************
*                                     BSP INTERRUPT DISABLE
*
* Arguments   : IntCont -  Specify which sub controller block to disable the interrupt on. Possible values: 0, 1, 2.
*                          where sub interrupt controller 0 is the main interrupt enable register
*             : IntNum  -  Specify which sub controller interrupt number to disable. Possible values: 0-31
*********************************************************************************************************
*/

void  BSP_IntDis (INT8U IntCont, INT8U IntNum)
{
    if (IntNum < 32) {
        switch (IntCont) {
            case 0:
                 MIC_ER &= ~(1 << IntNum);                                  /* Disable the IntNum on the main interrupt controller  */
                 break;

            case 1:
                 SIC1_ER &= ~(1 << IntNum);                                 /* Disable the IntNum on the sub interrupt controller 1 */
                 break;

            case 2:
                 SIC2_ER &= ~(1 << IntNum);                                 /* Disable the IntNum on the sub interrupt controller 2 */
                 break;
        }