📄 bsp.c.2006-04-14.12-44-15.4375
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/*
*********************************************************************************************************
* Philips LPC3000
* LPC2138 Kick Start Card Board Support Package
*
* (c) Copyright 2005, Micrium, Weston, FL
* All Rights Reserved
*
*
* File : BSP.C
* By : Eric Shufro
*********************************************************************************************************
*/
#define BSP_GLOBALS
#include <includes.h>
/*
*********************************************************************************************************
* CONSTANTS
*********************************************************************************************************
*/
#define BSP_UNDEF_INSTRUCTION_VECTOR_ADDR (*(INT32U *)0x00000004L)
#define BSP_SWI_VECTOR_ADDR (*(INT32U *)0x00000008L)
#define BSP_PREFETCH_ABORT_VECTOR_ADDR (*(INT32U *)0x0000000CL)
#define BSP_DATA_ABORT_VECTOR_ADDR (*(INT32U *)0x00000010L)
#define BSP_IRQ_VECTOR_ADDR (*(INT32U *)0x00000018L)
#define BSP_FIQ_VECTOR_ADDR (*(INT32U *)0x0000001CL)
#define BSP_IRQ_ISR_ADDR (*(INT32U *)0x00000038L)
#define BSP_FIQ_ISR_ADDR (*(INT32U *)0x0000003CL)
#define LED_1 (INT32U)(1 << 9)
#define LED_2 (INT32U)(1 << 10)
/*
*********************************************************************************************************
* DATA
*********************************************************************************************************
*/
INT8U const BSP_BitIxTbl[256] = {
0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, /* 0x00 to 0x0F */
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, /* 0x10 to 0x1F */
5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, /* 0x20 to 0x2F */
5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, /* 0x30 to 0x3F */
6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, /* 0x40 to 0x4F */
6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, /* 0x50 to 0x5F */
6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, /* 0x60 to 0x6F */
6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, /* 0x70 to 0x7F */
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, /* 0x80 to 0x8F */
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, /* 0x90 to 0x9F */
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, /* 0xA0 to 0xAF */
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, /* 0xB0 to 0xBF */
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, /* 0xC0 to 0xCF */
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, /* 0xD0 to 0xDF */
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, /* 0xE0 to 0xEF */
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, /* 0xF0 to 0xFF */
};
/*
*********************************************************************************************************
* VARIABLES
*********************************************************************************************************
*/
INT32U Tmr_ReloadCnts; /* Global variable for OS Ticker Match Compare Value */
PFNCT BSP_IntVectTbl[3][32]; /* Array of function pointers to ISR Handler */
/*
*********************************************************************************************************
* PROTOTYPES
*********************************************************************************************************
*/
static void BSP_PLL_Init(void);
static void Tmr_TickInit(void);
static INT8U BSP_Get_HighOrderBit(INT32U reg_val);
/*
*********************************************************************************************************
* BSP INITIALIZATION
*
* Description : This function should be called by your application code before you make use of any of the
* functions found in this module.
*
* Arguments : none
*********************************************************************************************************
*/
void BSP_Init (void)
{
INT8U i;
BOOT_MAP = 1; /* Remap IRAM to address 0x00 */
BSP_IRQ_VECTOR_ADDR = 0xE59FF018; /* LDR PC,[PC,#0x18] instruction */
BSP_IRQ_ISR_ADDR = (INT32U)OS_CPU_IRQ_ISR; /* IRQ exception vector address */
BSP_FIQ_VECTOR_ADDR = 0xE59FF018; /* LDR PC,[PC,#0x18] instruction */
BSP_FIQ_ISR_ADDR = (INT32U)OS_CPU_FIQ_ISR; /* FIQ exception vector address */
BSP_UNDEF_INSTRUCTION_VECTOR_ADDR = 0xEAFFFFFE; /* Jump to itself */
BSP_SWI_VECTOR_ADDR = 0xEAFFFFFE;
BSP_PREFETCH_ABORT_VECTOR_ADDR = 0xEAFFFFFE;
BSP_DATA_ABORT_VECTOR_ADDR = 0xEAFFFFFE;
BSP_FIQ_VECTOR_ADDR = 0xEAFFFFFE;
for (i = 0; i < 32; i++) { /* Initialize the Interrupt Handler lookup table */
BSP_IntVectTbl[0][i] = (PFNCT)0;
BSP_IntVectTbl[1][i] = (PFNCT)0;
BSP_IntVectTbl[2][i] = (PFNCT)0;
}
BSP_PLL_Init(); /* Initialize the PLL */
LED_Init(); /* Initialize the I/Os for the LED controls */
Tmr_TickInit(); /* Initialize the uC/OS-II tick interrupt */
}
/*
*********************************************************************************************************
* Set the CPU Clock Frequency
*
* Description: This function sets up and activates the PLL that drives the peripherals and cpu core.
*
* Notes : 1) PLL Output frequency when in DIRECT MODE, HCLKPLL_CTRL[15:14] = '01', is calculated by:
* FCLKOUT = (M * FCLKIN) / N
*
* 2) FCLKIN = CPU_OSC_FREQ = 13MHZ CRYSTAL ON THE LPC3000 EVALUATION BOARD by Philips
*
* 3) PLL SUMMARY
* FCLKOUT = ((46 * 13MHZ) / 3) = 199.33MHZ
* HCLK = (FCLKOUT / HCLK Divider) = (199.33 / 2) = 99.66MHZ
* PERIPH_CLK = (FCLKOUT / PERIPH_CLK Divider) = (199.33 / 16) = 12.46MHZ
*
* NOTE: DO NOT CHANGE THE PERIPHERAL DIVIDER TO 1 if OS-View
* is configued to use a high-speed UART. This is due to the
* fact that the high-speed UART divider cannot reach lower
* baud rates (38,400) when the PERIPH_CLK is running at 199MHZ.
* However, a FCLKOUT divided by 2, this baud rate can be set.
*
* 4) WARNING: HCLK must never exceed 104MHZ!
*
* 5) Clock Chain Relationships
* 1) OSC_CLK is called SYSCLK when SYSCLK_CTRL[0] = '0'.
* 2) OSC_CLK is selected for SYSCLK (shown above), then feeds into the HCLK_PLL.
* 3) The output of the HCLK_PLL is called FCLKOUT.
* 4) By setting PWR_CTRL[2], the PERIPH_CLK = FCLKOUT / PERIPH_CLK Divider,
* and, HCLK COULD be selected as FCLKOUT / HCLK Divider. The HCLK Divider is set by HCLKDIV_CTRL[1:0] which is set for 2.
* 5) By setting PWR_CTRL[10], the HCLK IS selected as FCLKOUT / HCLK Divider. (As opposed to being from PERIPH_CLK)
* Additionally, ARMCLK = FCLKOUT.
* 7) When everything is done, three clocks exist: HCLK, PERIPH_CLK, and ARMCLK and their values are shown above.
*
* PLL Definitions
* FCLKIN the frequency of the PLL input clock, we know from above that this equals SYSCLK = OSCCLK.
* FCLKOUT the output frequency of the PLL, we know from above that this is also called HCLK.
* N PLL pre-divider setting based on the bits in the relevant control register. N can have the values 1, 2, 3, or 4.
* M PLL feedback divider setting based on bits in the relevant control register. M is an integer from 1 through 256.
* P PLL post-divider setting based on the bits in the relevant control register. P can have the values 1, 2, 4, or 8.
*********************************************************************************************************
*/
void BSP_PLL_Init (void)
{
INT32U HCLKDiv;
PWR_CTRL = 0x00000012; /* Ensure that PWR_CTRL is reset with its initial value */
/* This way we are in a known mode after a warm reboot */
SYSCLK_CTRL &= ~(1 << 0); /* Ensure the SYSCLK MUX selects the Main OSC as SYSCLK */
HCLKDiv = (0x1F << 2); /* Define the Peripheral Clock Divider bit mask [6:2] */
HCLKDIV_CTRL &= ~HCLKDiv; /* Clear the Periph. Clk Divider bits ensuring defaults */
HCLKDIV_CTRL |= (0x0F << 2); /* Set HCLKDIV_CTRL[6:2] = 15, which divides by 16 */
HCLKDIV_CTRL |= (1 << 0); /* Set the HCLK divider bits (HCLK = FCKOUT / 2) */
/* [06:02] Peripheral Clk Div = (0 + 1) */
/* [01:00] HCLK Divider Control, (HCLK = FCKOUT / 2) */
HCLKPLL_CTRL = 0x645A; /* Set divider ratios (200mhz output), M=46, N=3, P=1 */
/* [16:16] PLL Power Down = 0, PLL in power down mode */
/* [15:15] Bypass Control = 0, CC0 Clk sent to post div */
/* [14:14] CCO clock = PLL CLK, bypassing post divider */
/* [13:13] Feedback Divider clocked by PLL_CLKOUT */
/* [12:11] PLL Post Divider (P) = 0 + 1 */
/* [10:09] PLL Pre Divider (N) = 2 + 1 */
/* [08:01] PLL Feedback Divider (M) = 45 + 1 */
/* [00:00] PLL Locked Status, 1 = locked (Read Only) */
PWR_CTRL &= ~(1 << 10); /* Set HCLK to be derived by FCKOUT / HCK Divider */
HCLKPLL_CTRL |= (1 << 16); /* Power up PLL */
while ((HCLKPLL_CTRL & (1 << 0)) == 0) { /* Wait for PLL to Lock */
;
}
PWR_CTRL |= (1 << 2); /* Enter Normal Run mode */
}
/*
*********************************************************************************************************
* Get the HCLK PLL frequency, FCLKOUT
* In this particular case, this is also the ARMCLK
*
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