genxlib_arch.vhd

基于FPGA的YUV转换RGB的色度空间转换

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-- Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
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-- This copyright and support notice must be retained as part
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--------------------------------------------------------------------------------
--
-- Filename - GenXlib_arch.vhd
-- Author - WC, Xilinx
-- Creation - 1 Oct 2005
--
-- Description -
--
--
-- $RCSfile: GenXlib_arch.vhd,v $ $Revision: 1.7 $ $Date: 2006/03/10 18:46:54 $
-- 
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-- *********************************************
--  *0000*  Delay Macro
--  delay
--
-- *********************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- This delay module does not have SCLR input pin: suitable for delay matching data-path components
-- where SCLR is not critical. Having no SCLR allows SRL16 based implementation in S, V, V2, V2P and V4.

entity delay is
  generic (
    width : integer :=16;
    delay : integer :=8;
    vector: integer :=1);
  port (
    clk   : in std_logic;    
    ce    : in std_logic;
    d1    : in std_logic := '0';
    q1    : out std_logic;
    d     : in std_logic_vector(width-1 downto 0) := (others => '0');
    q     : out std_logic_vector(width-1 downto 0));
end delay;

architecture RTL of delay is
  constant zeros : std_logic_vector(width-1 downto 0) := (others => '0');
  signal d_i: std_logic_vector(width-1 downto 0);
  signal q_i: std_logic_vector(width-1 downto 0);

  begin

    vect: if (vector=1) generate
      d_i <= d;
      q   <= q_i;
    end generate;
    
    sgnal: if (vector/=1) generate
      d_i(0) <= d1;
      q1     <= q_i(0);
    end generate;

    connect: if (delay<1) generate
      q_i <= d_i;
    end generate;
    
    needs_delay: if (delay>0) generate
      clk_process: process(clk)
        type delay_array is array (delay downto 1) of std_logic_vector(width-1 downto 0);
        variable shift_register : delay_array := (others => zeros);
        begin
          if (clk'event and clk = '1') then
            if (ce = '1') then
              for i in delay-1 downto 1 loop
                shift_register(i+1) := shift_register(i);
              end loop;
            shift_register(1) := d_i;
          end if;
        end if;
  
      q_i <= shift_register(delay);
      end process;
    end generate;
end RTL;

-- *********************************************
--  *0001*  Delay with synchronous clear Macro
--  delay_sclr
--
-- *********************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;  

-- This delay module has SCLR input pin: suitable for delaying control-path components
-- where SCLR is essential. Also synthsis can suck this component into BRAM, mult18x18s and DSP48.

entity delay_sclr is
  generic (
    width : integer :=16;  
    delay : integer :=1 );
  port (
    clk   : in std_logic;    
    ce    : in std_logic;    
    sclr  : in std_logic;    
    d     : in std_logic_vector(width-1 downto 0);
    q     : out std_logic_vector(width-1 downto 0));
end delay_sclr;

architecture RTL of delay_sclr is
constant zeros : std_logic_vector(width-1 downto 0) := (others => '0');
begin

  connect: if (delay<1) generate
    q <= d;
  end generate;
  
  needs_delay: if (delay>0) generate
    clk_process: process(clk)
      type delay_array is array (delay downto 1) of std_logic_vector(width-1 downto 0);
      variable shift_register : delay_array := (others => zeros);
      begin
        if (clk'event and clk = '1') then
          if (sclr = '1') then shift_register(delay downto 1) := (others => zeros);
            elsif (ce = '1') then
            for i in delay-1 downto 1 loop
              shift_register(i+1) := shift_register(i);
            end loop;
          shift_register(1) := d;
        end if;
      end if;

    q <= shift_register(delay);
    end process;
  end generate;
end RTL;

-- *********************************************
--  *0002*  radd_sub_sclr Macro
--  radd_sub_sclr
--
--  Module can be implemented in DSP48
--
-- ********************************************* 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;   
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

-- This radd_sub_sclr module will be implemented in DSP48.
entity radd_sub_sclr_yes is
  generic (
    width   : integer :=16;
    delay   : integer := 1;   -- This parameter allows the syntheser to break the 
                              -- carry chain if delay is >1. In DSP48s, it allows 
    add     : boolean :=true; -- registering A|B and C input ports.
    a_signed: boolean :=true; -- 1 when operand 'a' is signed
    b_signed: boolean :=true);-- 1 when operand 'b' is signed
  port (
    clk   : in std_logic;    
    ce    : in std_logic;       
    c_in  : in std_logic;
    a     : in std_logic_vector(width-1 downto 0);
    b     : in std_logic_vector(width-1 downto 0);
    s     : out std_logic_vector(width downto 0);
    sclr  : in std_logic);

  attribute register_balancing: string; 
  attribute register_balancing of radd_sub_sclr_yes: entity is "yes";
  attribute use_dsp48: string; 
  attribute use_dsp48 of radd_sub_sclr_yes: entity is "yes"; 
    
end radd_sub_sclr_yes;

architecture rtl of radd_sub_sclr_yes is
  signal c    : std_logic_vector(width downto 0);
  signal a_ext: std_logic := '0';
  signal b_ext: std_logic := '0';
begin

  sgn_a: if a_signed generate a_ext <= a(width-1); end generate;
  sgn_b: if b_signed generate b_ext <= b(width-1); end generate;

  adder: if add      generate c <= (a_ext & a) + (b_ext & b) + c_in; end generate;
  subtr: if not add  generate c <= (b_ext & b) - (a_ext & a) - c_in; end generate;

  reg : entity work.delay_sclr(rtl) 
    generic map ( width => width+1, delay => delay)   
    port map ( clk => clk, ce => ce, sclr => sclr, d => c, q => s);

end rtl;

-- This radd_sub_sclr module will be implemented in fabric.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;   
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity radd_sub_sclr_no is
  generic (
    width   : integer :=16;
    delay   : integer := 1;   -- This parameter allows the syntheser to break the 
                              -- carry chain if delay is >1. In DSP48s, it allows 
    add     : boolean :=true; -- registering A|B and C input ports.
    a_signed: boolean :=true; -- 1 when operand 'a' is signed
    b_signed: boolean :=true);-- 1 when operand 'b' is signed
  port (
    clk   : in std_logic;    
    ce    : in std_logic;       
    c_in  : in std_logic;
    a     : in std_logic_vector(width-1 downto 0);
    b     : in std_logic_vector(width-1 downto 0);
    s     : out std_logic_vector(width downto 0);
    sclr  : in std_logic);

  attribute register_balancing: string; 
  attribute register_balancing of radd_sub_sclr_no: entity is "yes";
  attribute use_dsp48: string; 
  attribute use_dsp48 of radd_sub_sclr_no: entity is "no"; 
    
end radd_sub_sclr_no;

architecture rtl of radd_sub_sclr_no is
  signal c    : std_logic_vector(width downto 0);
  signal a_ext: std_logic := '0';
  signal b_ext: std_logic := '0';
begin

  sgn_a: if a_signed generate a_ext <= a(width-1); end generate;
  sgn_b: if b_signed generate b_ext <= b(width-1); end generate;

  adder: if add      generate c <= (a_ext & a) + (b_ext & b) + c_in; end generate;
  subtr: if not add  generate c <= (b_ext & b) - (a_ext & a) - c_in; end generate;

  reg : entity work.delay_sclr(rtl) 
    generic map ( width => width+1, delay => delay)   
    port map ( clk => clk, ce => ce, sclr => sclr, d => c, q => s);

end rtl;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;   
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

-- This radd_sub_sclr module will be implemented in either fabric or DSP48.
entity radd_sub_sclr is
  generic (
    width   : integer :=16;
    delay   : integer := 1;   -- This parameter allows the syntheser to break the 
    fabric  : integer := 1;   -- carry chain if delay is >1. In DSP48s, it allows 
    add     : boolean :=true; -- registering A|B and C input ports.
    a_signed: boolean :=true; -- 1 when operand 'a' is signed
    b_signed: boolean :=true);-- 1 when operand 'b' is signed
  port (
    clk   : in std_logic;    
    ce    : in std_logic;       
    c_in  : in std_logic;
    a     : in std_logic_vector(width-1 downto 0);
    b     : in std_logic_vector(width-1 downto 0);
    s     : out std_logic_vector(width downto 0);
    sclr  : in std_logic);
    
end radd_sub_sclr;

architecture rtl of radd_sub_sclr is

begin

  use_dsp48 : if( fabric = 0 ) generate
    adder : entity work.radd_sub_sclr_yes(rtl) 
    generic map ( width => width, delay => delay, add => add, a_signed => a_signed, b_signed => b_signed )   
    port map ( clk => clk, ce => ce, c_in => c_in, a => a, b => b, s => s, sclr => sclr );
  end generate;

  use_fabric : if( fabric /= 0 ) generate
    adder : entity work.radd_sub_sclr_no(rtl) 
    generic map ( width => width, delay => delay, add => add, a_signed => a_signed, b_signed => b_signed )   
    port map ( clk => clk, ce => ce, c_in => c_in, a => a, b => b, s => s, sclr => sclr );
  end generate;
  
end rtl;

-- *********************************************
--  *0003*  NON-SATURATING, unbiased round macro
--  get_round_addend
--
--  This macro implements round towards inf, zero, or biased 
--
--  Biased round : 0.5 rounds up 
--  Round towards zero: 0.5 rounds up when integer part is negative, rounds down when positive