📄 xil_rgb2ycrcb_tb.mdl
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SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Unsigned"
n_bits "1"
bin_pt "0"
quantization "Round (unbiased: +/- Inf)"
overflow "Saturate"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "20,20,356,345"
block_type "gatewayin"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "55,22,1,1,white,yellow,0,4bb76ffd"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In "
"','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','C"
"OMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this lin"
"e -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "HS_o"
Ports [1, 1]
Position [425, 434, 480, 456]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed point"
" inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Ha"
"rdware notes: In hardware these blocks become top level output ports or are "
"discarded, depending on how they are configured."
hdl_port on
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "20,20,356,327"
block_type "gatewayout"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "55,22,1,1,white,yellow,0,f0cec300"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,' ');\ncolor('black');por"
"t_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','"
"COMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this li"
"ne -- machine generated code. ');\n"
}
Block {
BlockType SubSystem
Name "More Info"
Ports []
Position [405, 31, 530, 109]
DropShadow on
ShowName off
FontName "Arial"
FontSize 12
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
MaskDisplay "disp('Double click\\n for\\n more information.'"
")"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
System {
Name "More Info"
Location [760, 234, 1394, 1003]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Annotation {
Name "For detailed information on color space con"
"version and on\nthis R-G-B to Y-Pr-Pb converter design, see Andy Miller's \n "
"\"Colour Space Conversion\" articles at support.xilinx.com:\n\n http://www.su"
"pport.xilinx.com/support/techxclusives/techX-home.htm"
Position [20, 40]
HorizontalAlignment "left"
VerticalAlignment "top"
UseDisplayTextAsClickCallback off
FontName "Arial"
FontSize 12
}
Annotation {
Name "Color SpaceConversion Image Processing Demo"
"nstration"
Position [208, 22]
UseDisplayTextAsClickCallback off
FontName "Arial"
FontSize 14
FontWeight "bold"
}
}
}
Block {
BlockType Reference
Name "P_EN_i"
Ports [1, 1]
Position [150, 409, 205, 431]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Unsigned"
n_bits "1"
bin_pt "0"
quantization "Round (unbiased: +/- Inf)"
overflow "Saturate"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "20,20,356,345"
block_type "gatewayin"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "55,22,1,1,white,yellow,0,4bb76ffd"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In "
"','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','C"
"OMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this lin"
"e -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "Pix_en_o"
Ports [1, 1]
Position [425, 494, 480, 516]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed point"
" inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Ha"
"rdware notes: In hardware these blocks become top level output ports or are "
"discarded, depending on how they are configured."
hdl_port on
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "20,20,356,327"
block_type "gatewayout"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "55,22,1,1,white,yellow,0,f0cec300"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,' ');\ncolor('black');por"
"t_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','"
"COMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this li"
"ne -- machine generated code. ');\n"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator"
Ports [0, 1]
Position [75, 313, 120, 347]
ShowName off
Period "100000"
}
Block {
BlockType Reference
Name "R"
Ports [1, 1]
Position [150, 184, 205, 206]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Unsigned"
n_bits "10"
bin_pt "2"
quantization "Round (unbiased: +/- Inf)"
overflow "Saturate"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "20,20,356,414"
block_type "gatewayin"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "55,22,1,1,white,yellow,0,4bb76ffd"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In "
"','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','C"
"OMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this lin"
"e -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "Signal From\nWorkspace1"
Ports [0, 1]
Position [40, 178, 120, 212]
ShowName off
SourceBlock "dspsrcs4/Signal From\nWorkspace"
SourceType "Signal From Workspace"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
X "input_image_r"
Ts "1"
nsamps "1"
OutputAfterFinalValue "Setting to zero"
ignoreOrWarnInputAndFrameLengths off
}
Block {
BlockType Reference
Name "Signal From\nWorkspace2"
Ports [0, 1]
Position [40, 223, 120, 257]
ShowName off
SourceBlock "dspsrcs4/Signal From\nWorkspace"
SourceType "Signal From Workspace"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
X "input_image_g"
Ts "1"
nsamps "1"
OutputAfterFinalValue "Setting to zero"
ignoreOrWarnInputAndFrameLengths off
}
Block {
BlockType Reference
Name "Signal From\nWorkspace3"
Ports [0, 1]
Position [40, 268, 120, 302]
ShowName off
SourceBlock "dspsrcs4/Signal From\nWorkspace"
SourceType "Signal From Workspace"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
X "input_image_b"
Ts "1"
nsamps "1"
OutputAfterFinalValue "Setting to zero"
ignoreOrWarnInputAndFrameLengths off
}
Block {
BlockType Reference
Name "Signal To\nWorkspace"
Ports [1]
Position [510, 187, 575, 223]
ShowName off
FontName "Arial"
SourceBlock "dspsnks4/Signal To\nWorkspace"
SourceType "Signal To Workspace"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
VariableName "data_out_y"
MaxDataPoints "inf"
Decimation "1"
FrameMode "Concatenate frames (2-D array)"
FixptAsFi off
}
Block {
BlockType Reference
Name "Signal To\nWorkspace1"
Ports [1]
Position [510, 247, 575, 283]
ShowName off
FontName "Arial"
SourceBlock "dspsnks4/Signal To\nWorkspace"
SourceType "Signal To Workspace"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
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