📄 xil_rgb2ycrcb_tb.mdl
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Cell "DefineNamingRule"
Cell "SignalNamingRule"
Cell "ParamNamingRule"
Cell "InlinedPrmAccess"
Cell "CustomSymbolStr"
PropName "DisabledProps"
}
Version "1.2.0"
ForceParamTrailComments off
GenerateComments on
IgnoreCustomStorageClasses on
IncHierarchyInIds off
MaxIdLength 31
PreserveName off
PreserveNameWithParent off
ShowEliminatedStatement off
IncAutoGenComments off
SimulinkDataObjDesc off
SFDataObjDesc off
IncDataTypeInIds off
PrefixModelToSubsysFcnNames on
MangleLength 1
CustomSymbolStrGlobalVar "$R$N$M"
CustomSymbolStrType "$N$R$M"
CustomSymbolStrField "$N$M"
CustomSymbolStrFcn "$R$N$M$F"
CustomSymbolStrBlkIO "rtb_$N$M"
CustomSymbolStrTmpVar "$N$M"
CustomSymbolStrMacro "$R$N$M"
DefineNamingRule "None"
ParamNamingRule "None"
SignalNamingRule "None"
InsertBlockDesc off
SimulinkBlockComments on
EnableCustomComments off
InlinedPrmAccess "Literals"
ReqsInCode off
}
Simulink.GRTTargetCC {
$BackupClass "Simulink.TargetCC"
$ObjectID 10
Array {
Type "Cell"
Dimension 12
Cell "IncludeMdlTerminateFcn"
Cell "CombineOutputUpdateFcns"
Cell "SuppressErrorStatus"
Cell "ERTCustomFileBanners"
Cell "GenerateSampleERTMain"
Cell "MultiInstanceERTCode"
Cell "PurelyIntegerCode"
Cell "SupportNonFinite"
Cell "SupportComplex"
Cell "SupportAbsoluteTime"
Cell "SupportContinuousTime"
Cell "SupportNonInlinedSFcns"
PropName "DisabledProps"
}
Version "1.2.0"
TargetFcnLib "ansi_tfl_tmw.mat"
TargetLibSuffix ""
TargetPreCompLibLocation ""
GenFloatMathFcnCalls "ANSI_C"
UtilityFuncGeneration "Auto"
GenerateFullHeader on
GenerateSampleERTMain off
GenerateTestInterfaces off
IsPILTarget off
ModelReferenceCompliant on
IncludeMdlTerminateFcn on
CombineOutputUpdateFcns off
SuppressErrorStatus off
IncludeFileDelimiter "Auto"
ERTCustomFileBanners off
SupportAbsoluteTime on
LogVarNameModifier "rt_"
MatFileLogging on
MultiInstanceERTCode off
SupportNonFinite on
SupportComplex on
PurelyIntegerCode off
SupportContinuousTime on
SupportNonInlinedSFcns on
EnableShiftOperators on
ParenthesesLevel "Nominal"
ExtMode off
ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
GenerateASAP2 off
}
PropName "Components"
}
}
PropName "Components"
}
Name "Configuration"
SimulationMode "normal"
CurrentDlgPage "Solver"
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
}
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Constant
}
Block {
BlockType DiscretePulseGenerator
PulseType "Sample based"
TimeSource "Use simulation time"
Amplitude "1"
Period "2"
PulseWidth "1"
PhaseDelay "0"
SampleTime "1"
VectorParams1D on
}
Block {
BlockType FrameConversion
OutFrame "Frame based"
}
Block {
BlockType FromWorkspace
VariableName "simulink_input"
SampleTime "-1"
Interpolate on
ZeroCross off
OutputAfterFinalValue "Extrapolation"
}
Block {
BlockType Inport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchByCopyingInsideSignal off
Interpolate on
}
Block {
BlockType Mux
Inputs "4"
DisplayOption "none"
UseBusObject off
BusObject "BusObject"
NonVirtualBus off
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Reference
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Terminator
}
Block {
BlockType ToWorkspace
VariableName "simulink_output"
MaxDataPoints "1000"
Decimation "1"
SampleTime "0"
FixptAsFi off
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "Xil_RGB2YCrCb_tb"
Location [569, 124, 1175, 724]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name " System Generator"
Tag "genX"
Ports []
Position [77, 56, 128, 106]
ShowName off
AttributesFormatString "System\\nGenerator"
UserDataPersistent on
UserData "DataTag0"
SourceBlock "xbsIndex_r4/ System Generator"
SourceType "Xilinx System Generator Block"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
infoedit " System Generator"
xilinxfamily "Virtex4"
part "xc4vsx35"
speed "-10"
package "ff668"
synthesis_tool "XST"
directory "./netlist"
testbench off
simulink_period "1"
sysclk_period "10"
incr_netlist off
trim_vbits "Everywhere in SubSystem"
dbl_ovrd "According to Block Masks"
core_generation "According to Block Masks"
run_coregen off
deprecated_control off
eval_field "0"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "sysgen"
block_version "8.2.01"
sg_icon_stat "51,50,-1,-1,red,beige,0,07734"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npa"
"tch([0 51 51 0 ],[0 0 50 50 ],[0.93 0.92 0.86]);\npatch([12 4 16 4 12 25 29 3"
"3 47 36 25 17 29 17 25 36 47 33 29 25 12 ],[5 13 25 37 45 45 41 45 45 34 45 3"
"7 25 13 5 16 5 5 9 5 5 ],[0.6 0.2 0.25]);\nplot([0 0 51 51 0 ],[0 50 50 0 0 ]"
");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin ico"
"n text');\nfprintf('','COMMENT: end icon text');\n"
sg_blockgui_xml "<!-- * Copyright (c) 2005, Xilinx, Inc. All "
"Rights Reserved. --><!-- * Reproduction or reuse, in any form, w"
"ithout the explicit written --><!-- * consent of Xilinx, Inc., is strictly"
" prohibited. --><sysgenblock has_userdata=\"true\" tag=\"gen"
"X\" block_type=\"sysgen\" simulinkname=\" System Generator\" >\n <icon width="
"\"51\" bg_color=\"beige\" height=\"50\" caption_format=\"System\\nGenerator\""
" wmark_color=\"red\" />\n <callbacks DeleteFcn=\"xlSysgenGUI('delete', gcs, g"
"cbh);\" OpenFcn=\"xlSysgenGUI('startup',gcs,gcbh)\" ModelCloseFcn=\"xlSysgenG"
"UI('Close',gcs,gcbh)\" PostSaveFcn=\"xlSysgenGUI('Save')\" />\n <libraries>\n"
" <library name=\"xbsIndex\" />\n <library name=\"xbsBasic\" />\n <library "
"name=\"xbsTools\" />\n </libraries>\n <subsystem_model file=\"system_generato"
"r_subsystem.mdl\" />\n <blockgui label=\"Xilinx System Generator\" >\n <edit"
"box evaluate=\"false\" multi_line=\"true\" name=\"infoedit\" read_only=\"true"
"\" default=\" System Generator\" />\n <editbox evaluate=\"false\" name=\"xil"
"inxfamily\" default=\"Virtex4\" label=\"Xilinx family\" />\n <editbox evalua"
"te=\"false\" name=\"part\" default=\"xc4vsx35\" label=\"Part\" />\n <editbox"
" evaluate=\"false\" name=\"speed\" default=\"-10\" label=\"Speed\" />\n <edi"
"tbox evaluate=\"false\" name=\"package\" default=\"ff668\" label=\"Package\" "
"/>\n <listbox evaluate=\"true\" name=\"synthesis_tool\" default=\"XST\" labe"
"l=\"Synthesis tool\" >\n <item value=\"Spectrum\" />\n <item value=\"Synp"
"lify\" />\n <item value=\"Synplify Pro\" />\n <item value=\"XST\" />\n "
"<item value=\"Precision\" />\n </listbox>\n <editbox evaluate=\"false\" nam"
"e=\"directory\" default=\"./netlist\" label=\"Target directory\" />\n <check"
"box evaluate=\"true\" name=\"testbench\" default=\"off\" label=\"Testbench\" "
"/>\n <editbox evaluate=\"true\" name=\"simulink_period\" default=\"1\" label"
"=\"Simulink period\" />\n <editbox evaluate=\"true\" name=\"sysclk_period\" "
"default=\"10\" label=\"System clock period\" />\n <checkbox evaluate=\"true"
"\" name=\"incr_netlist\" default=\"off\" label=\"Incremental netlisting\" />"
"\n <listbox evaluate=\"true\" name=\"trim_vbits\" default=\"Everywhere in Su"
"bSystem\" label=\"Trim valid bits\" >\n <item value=\"According to Block Ma"
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