xil_rgb2ycrcb.vhd

基于FPGA的YUV转换RGB的色度空间转换

  end generate;
  
  del_G : entity work.delay(rtl) -- Delay matching: G is delayed so it arrives in sync with a * (R - G) and b * (B - G)  
    generic map ( 
      width => IWIDTH, 
      delay => MULT_ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS) + ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS) )   
    port map (
      clk   => clk,
      d     => G,  
      q     => y_intb(MWIDTH-4 downto MWIDTH-IWIDTH-3),
      ce    => ce);

  y_intb(MWIDTH-3) <= '0'; -- zero-padd G (as G is usigned) y_intb(MWIDTH-4);                
  y_intb(MWIDTH-IWIDTH-4 downto 0) <= (others => '0');  -- zero-padd G value so it can be added properly

  add_aRG_bBG_G : entity work.radd_sub_sclr(rtl)
    generic map ( 
      width => MWIDTH-2, 
      add   => true,
      fabric=> FABRIC_ADDS, 
      delay => ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS))   
    port map (
      clk   => clk,
      a     => y_inta,
      b     => y_intb,
      s     => y_int,
      c_in  => logic0,
      ce    => ce,
      sclr  => sclr);

--------------------------------------------------------------------
-- Create Cb = c(B-Y) and Cr = d(R-Y)
--------------------------------------------------------------------

  del_B : entity work.delay(rtl) -- Delay matching: B is delayed so it arrives in sync with y_int                                           
    generic map ( 
      width => IWIDTH, 
      delay => MULT_ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS) + 2*ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS) )   
    port map (
      clk   => clk,
      d     => B,  
      q     => b_int(MWIDTH-4 downto MWIDTH-3-IWIDTH),
      ce    => ce);

  b_int(MWIDTH-2) <= '0';                               -- zero padd MSBs of b, so the integer
  b_int(MWIDTH-3) <= '0';                               -- parts are aligned
  b_int(MWIDTH-4-IWIDTH downto 0) <= (others => '0');   -- zero padd b_int, so widths are equal

  del_R : entity work.delay(rtl)                                       
    generic map ( 
      width => IWIDTH, 
      delay => MULT_ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS) + 2*ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS) )   
    port map (
      clk   => clk,
      d     => R,  
      q     => r_int(MWIDTH-4 downto MWIDTH-3-IWIDTH),
      ce    => ce);

  r_int(MWIDTH-2) <= '0';                               -- zero padd MSBs of r, so the integer
  r_int(MWIDTH-3) <= '0';                               -- parts are aligned
  r_int(MWIDTH-4-IWIDTH downto 0) <= (others => '0');   -- zero padd r_int, so widths are equal

  sub_BY : entity work.radd_sub_sclr(rtl)   -- calculate (B - Y)
    generic map ( 
      width => MWIDTH-1, 
      add => false,
      fabric=> FABRIC_ADDS,
      delay => ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS))   
    port map (
      clk   => clk,
      a     => y_int,
      b     => b_int,
      s     => by,
      c_in  => logic0,
      ce    => ce,
      sclr  => sclr);

  sub_RY : entity work.radd_sub_sclr(rtl)   -- Calculate (R - Y)
    generic map ( 
      width => MWIDTH-1, 
      add   => false,
      fabric=> FABRIC_ADDS,
      delay => ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS))   
    port map (
      clk   => clk,
      a     => y_int,
      b     => r_int,
      s     => ry,
      c_in  => logic0,
      ce    => ce,
      sclr  => sclr);

  sp3_v2_v2p_mult23: if (FAMILY_HAS_MAC=0) generate
    mult_cBY: entity work.mult(rtl) -- Cb = d * (B - Y)
      generic map ( 
        iwidtha => MWIDTH, 
        iwidthb => CWIDTH,
        delay   => MULT_DELAY(FAMILY_HAS_MAC))   
      port map (
        clk     => clk,
        ce      => ce,
        sclr    => sclr,
        a       => by,
        b       => DCOEFvec,
        p       => cb_int);
  
    mult_dRY: entity work.mult(rtl)  -- Cr = c * (R - Y)
      generic map ( 
        iwidtha => MWIDTH, 
        iwidthb => CWIDTH,
        delay   => MULT_DELAY(FAMILY_HAS_MAC))   
      port map (
        clk     => clk,
        ce      => ce,
        sclr    => sclr,
        a       => ry,
        b       => CCOEFvec,
        p       => cr_int);

    -----------------------------------------------------
    -- Rounding and offset compensating the Chroma components
    -----------------------------------------------------
    round_Cb : entity work.round(rtl) -- Rounding and offset compensating Cb with one adder                                     
      generic map ( 
        iwidth     => MWIDTH+CWIDTH-2,
        owidth     => OWIDTH+2, 
        has_offset => 1,
        delay      => ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS) )   
      port map (
        a       => cb_int(MWIDTH+CWIDTH-3 downto 0),  
        offset  => COFFSETvec(OWIDTH+1 downto 0),
        ra      => cb_int_round,
        clk     => clk,
        ce      => ce,
        sclr    => sclr);
  
    round_Cr : entity work.round(rtl) -- Rounding and offset compensating Cr with one adder                                     
      generic map ( 
        iwidth => MWIDTH+CWIDTH-2,
        owidth => OWIDTH+2, 
        has_offset=> 1 )   
      port map (
        a       => cr_int(MWIDTH+CWIDTH-3 downto 0),  
        offset  => COFFSETvec(OWIDTH+1 downto 0),
        ra      => cr_int_round,
        clk     => clk,
        ce      => ce,
        sclr    => sclr);
  end generate;

  v4_mac23: if (FAMILY_HAS_MAC=1) generate
    mac_cBY: entity work.mac(rtl) -- Cb = round( d * (B - Y) + COFFSET)
      generic map (                   
        IWIDTHA   => MWIDTH, 
        IWIDTHB   => CWIDTH,   
        OWIDTH    => OWIDTH+4,        -- offset contains rounding const
        ROUND_MODE=> 0,
        HAS_C     => 1)
      port map (
        clk       => clk,
        ce        => ce,
        sclr      => sclr,
        a         => by,
        b         => DCOEFvec,
        c         => COFFSETvec,
        p         => cb_int(OWIDTH+3 downto 0));
    cb_int_round <= cb_int(OWIDTH+1 downto 0);

    mac_cRY: entity work.mac(rtl) -- Cb = round( c * (R - Y) + COFFSET)
      generic map (                   
        IWIDTHA   => MWIDTH, 
        IWIDTHB   => CWIDTH,   
        OWIDTH    => OWIDTH+4,        -- offset contains rounding const
        ROUND_MODE=> 0,
        HAS_C     => 1)
      port map (
        clk       => clk,
        ce        => ce,
        sclr      => sclr,
        a         => ry,
        b         => CCOEFvec,
        c         => COFFSETvec,
        p         => cr_int(OWIDTH+3 downto 0));
    cr_int_round <= cr_int(OWIDTH+1 downto 0);
  end generate;

-----------------------------------------------------
-- Rounding and offset compensating the Luma component
-----------------------------------------------------
  round_Y : entity work.round(rtl)  -- Rounding and offset compensating Y with one adder
    generic map ( 
      iwidth     => MWIDTH-1,
      owidth     => OWIDTH+2, 
      has_offset => 1,
      delay      => ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS))   
    port map (
      a       => y_int(MWIDTH-2 downto 0),  
      offset  => YOFFSETvec,
      ra      => y_int_round,
      clk     => clk,
      ce      => ce,
      sclr    => sclr);


  del_Y : entity work.delay(rtl)  -- Delay matching: y_int_round is delayed so it is in sync with cr_int_round and cb_int_round  
    generic map ( 
      width => OWIDTH+2, 
      delay => MULT_ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS) )   
    port map (
      clk   => clk,
      d     => y_int_round,  
      q     => y_int_delay,
      ce    => ce);    

-----------------------------------------------------
-- Clipping and clamping as necessary
-----------------------------------------------------
  clip: if (HAS_CLIP=1) generate
    max_Y : entity work.max_sat(rtl)  -- Add the logic to catch overflow saturation (max)
      generic map (width => OWIDTH+2)   
      port map (
        a     => y_int_delay,  
        max   => YMAXvec,
        ma    => y_int_postmax,
        clk   => clk,
        ce    => ce,
        sclr  => sclr);

    max_Cb : entity work.max_sat(rtl) -- Add the logic to catch overflow saturation (max)
      generic map (width => OWIDTH+2)   
      port map (
        a     => cb_int_round,  
        max   => CMAXvec,
        ma    => cb_int_postmax,
        clk   => clk,
        ce    => ce,
        sclr  => sclr);
  
    max_Cr : entity work.max_sat(rtl) -- Add the logic to catch overflow saturation (max)
      generic map (width => OWIDTH+2)   
      port map (
        a     => cr_int_round,  
        max   => CMAXvec,
        ma    => cr_int_postmax,
        clk   => clk,
        ce    => ce,
        sclr  => sclr); 
  end generate;
  
  no_clip: if (HAS_CLIP/=1) generate
    y_int_postmax  <= y_int_delay;
    cr_int_postmax <= cr_int_round;
    cb_int_postmax <= cb_int_round;
  end generate;

  clamp: if (HAS_CLAMP=1) generate
    min_Y : entity work.min_sat(rtl)   -- Add the logic to catch underflow saturation (min)
      generic map (width => OWIDTH+2)   
      port map (
        a     => y_int_postmax,  
        min   => YMINvec,
        ma    => y_int_postmin,
        clk   => clk,
        ce    => ce,
        sclr  => sclr);
  
    min_Cb : entity work.min_sat(rtl) -- Add the logic to catch underflow saturation (min)
      generic map (width => OWIDTH+2)   
      port map (
        a     => cb_int_postmax,
        min   => CMINvec,
        ma    => cb_int_postmin,
        clk   => clk,
        ce    => ce,
        sclr  => sclr);
  
    min_Cr : entity work.min_sat(rtl) -- Add the logic to catch underflow saturation (min)
      generic map (width => OWIDTH+2)   
      port map (
        a     => cr_int_postmax,
        min   => CMINvec,
        ma    => cr_int_postmin,
        clk   => clk,
        ce    => ce,
        sclr  => sclr);
  end generate;

  no_clamp: if (HAS_CLAMP/=1) generate
    y_int_postmin  <= y_int_postmax;
    cr_int_postmin <= cr_int_postmax;
    cb_int_postmin <= cb_int_postmax;
  end generate;
  
  Y   <=  y_int_postmin(OWIDTH-1 downto 0);
  Cb  <= cb_int_postmin(OWIDTH-1 downto 0);
  Cr  <= cr_int_postmin(OWIDTH-1 downto 0);

end rtl;