xil_rgb2ycrcb.vhd

基于FPGA的YUV转换RGB的色度空间转换

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--
-- Title - Xil_RGB2YCrCb.vhd
-- Author(s) - GZ & WCC, Xilinx
-- Creation - 7 Dec 2005
--
-- $RCSfile: Xil_RGB2YCrCb.vhd,v $ $Revision: 1.8 $ $Date: 2006/01/19 19:55:41 $
--
-- ************************************************************************
--  *008*   RGB2YCrCb Macro
--
-- Description: Color Space Converter (RGB to YCrCb)
--
-- Generalized conversion:
-- Y  =   |   AC    (1-AC-BC)    BC   |   |R|    |Yoffset| 
-- Cr = CC| (1-AC)  (AC+BC-1)   -BC   | * |G| +  |Coffset|
-- Cb = CD|  -AC    (AC+BC-1)  (1-BC) |   |B|    |Coffset|
--
--
-- Refactored format conversion:
-- Y  = AC*R + (1-AC-BC)*G + BC*B + Yoffset 
-- Cr = CC*(R-Y) +  Coffset
-- Cb = CD*(B-Y) +  Coffset

-- ITU 601 (SDTV):
-- if RGB data is between 0 and 255 
--
-- Y  =  0.299 * R' + 0.587 * G' + 0.114 * B' + 0   
-- Cr =  0.5   * R' - 0.419 * G' - 0.081 * B' + 0.5
-- Cb = -0.169 * R' - 0.331 * G' + 0.5   * B' + 0.5
--
---------------------------------------------------------------------
-- Refactoring:
-- if RGB data is between 0 and 255 (R'G'B' are gamma corrected)
--
-- Y   = 0.299 * (R' - G') + G' + 0.114 * (B' - G') 
-- Cr  = 0.713 * (R' - Y') + 0.5
-- Cb  = 0.564 * (B' - Y') + 0.5
--
-- ******************************************************************  
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all; 

LIBRARY work;
USE work.color_space_pkg.all;

LIBRARY work;
USE work.genxlib_utils.ALL;

entity Xil_RGB2YCrCb is   
  generic ( 
    FAMILY_HAS_MAC: integer:= 1;
    FABRIC_ADDS   : integer:= 1; -- Adders are implemented using logic fabric based adders
    IWIDTH        : integer:= 9;
    CWIDTH        : integer:= 17; -- Coefficients are unsigned
    MWIDTH        : integer:= 17;   -- Width of (B' - Y'_601) and (R' - Y'_601) data (data width at CCOEF and DCOEF multipliers)
    OWIDTH        : integer:= 9;
    YMAX          : integer:= 255;
    YMIN          : integer:= 0;
    CMAX          : integer:= 255;
    CMIN          : integer:= 0;
    YOFFSET       : integer:= 0;
    COFFSET       : integer:= 128;    -- represent 0.5 in 9.7 format
    ACOEF         : integer:= 613;    -- 0.29931
    BCOEF         : integer:= 233;    -- 0.11376953125
    CCOEF         : integer:= 1460;   -- 0.712890625
    DCOEF         : integer:= 1155;   -- 0.56396484375
    HAS_CLIP      : integer:= 1; 
    HAS_CLAMP     : integer:= 1); 
  port (                               
    Y             : out std_logic_vector(OWIDTH-1 downto 0);  -- Y  = a(R-G) + G + b(B-G)
    Cr            : out std_logic_vector(OWIDTH-1 downto 0);  -- Cr = d(R-Y)  
    Cb            : out std_logic_vector(OWIDTH-1 downto 0);  -- Cb = c(B-Y)
    R             : in std_logic_vector(IWIDTH-1 downto 0);   
    G             : in std_logic_vector(IWIDTH-1 downto 0);
    B             : in std_logic_vector(IWIDTH-1 downto 0);
    V_SYNC_in     : in std_logic := '0';
    H_SYNC_in     : in std_logic := '0';
    PIX_EN_in     : in std_logic := '1';
    V_SYNC_out    : out std_logic;
    H_SYNC_out    : out std_logic;
    PIX_EN_out    : out std_logic;
    clk           : in std_logic;
    ce            : in std_logic := '1';
    sclr          : in std_logic := '0');
end Xil_RGB2YCrCb;    

architecture rtl of Xil_RGB2YCrCb is            

--  constant ACOEFF_RANGE   : integer := CWIDTH-1 - LOG2_BASE( ACOEF ); -- Leading zeros in coeff values
--  constant BCOEFF_RANGE   : integer := CWIDTH-1 - LOG2_BASE( BCOEF ); 

  constant MODULE_LATENCY : integer := RGB2YCrCb_LATENCY(FAMILY_HAS_MAC, FABRIC_ADDS, HAS_CLIP, HAS_CLAMP); -- ADDER_DELAY is set to 1, MULT_DELAY is 2
  constant YOFFSETvec     : std_logic_vector(OWIDTH+1 downto 0) := conv_std_logic_vector(YOFFSET,OWIDTH+2);
  constant COFFSETvec     : std_logic_vector(OWIDTH+3 downto 0) := conv_std_logic_vector(COFFSET,OWIDTH+4);
  constant ACOEFvec       : std_logic_vector(CWIDTH-1 downto 0) := conv_std_logic_vector(ACOEF, CWIDTH); --     ACOEF SRL ACOEFF_RANGE, CWIDTH); -- ACOEFF constant is normalized
  constant BCOEFvec       : std_logic_vector(CWIDTH-1 downto 0) := conv_std_logic_vector(BCOEF, CWIDTH); --     BCOEF SRL BCOEFF_RANGE, CWIDTH); -- BCOEFF constant is normalized
  constant CCOEFvec       : std_logic_vector(CWIDTH-1 downto 0) := conv_std_logic_vector(CCOEF,CWIDTH);
  constant DCOEFvec       : std_logic_vector(CWIDTH-1 downto 0) := conv_std_logic_vector(DCOEF,CWIDTH);
  constant YMAXvec        : std_logic_vector(OWIDTH+1 downto 0) := conv_std_logic_vector(YMAX,OWIDTH+2);
  constant YMINvec        : std_logic_vector(OWIDTH+1 downto 0) := conv_std_logic_vector(YMIN,OWIDTH+2);
  constant CMAXvec        : std_logic_vector(OWIDTH+1 downto 0) := conv_std_logic_vector(CMAX,OWIDTH+2);
  constant CMINvec        : std_logic_vector(OWIDTH+1 downto 0) := conv_std_logic_vector(CMIN,OWIDTH+2);

-- This is the delay of a virtex4 multiplier followed by a rounder. In order to facilitate
-- grouping the rounder with the mult into the same DSP48, overall latency must be 2
  constant MULT_ROUND_DELAY : integer := 3-FAMILY_HAS_MAC;

-- Low level constants 
  constant logic0         : std_logic := '0';
  constant logic1         : std_logic := '1';

-- signal declarations
  signal rg               : std_logic_vector(IWIDTH downto 0);
  signal bg               : std_logic_vector(IWIDTH downto 0);  
  signal rgm              : std_logic_vector(IWIDTH+CWIDTH downto 0);
  signal bgm              : std_logic_vector(IWIDTH+CWIDTH downto 0);
--signal rgm_norm         : std_logic_vector(MWIDTH-4 downto 0); -- MWIDTH-3 bits wide, normalized
--signal bgm_norm         : std_logic_vector(MWIDTH-4 downto 0); -- MWIDTH-3 bits wide, normalized
  signal y_inta_raw       : std_logic_vector(IWIDTH+CWIDTH downto 0); -- Only for the DSP48 based implementation
  signal y_inta           : std_logic_vector(MWIDTH-3 downto 0);  
  signal y_intb           : std_logic_vector(MWIDTH-3 downto 0);
  signal y_int            : std_logic_vector(MWIDTH-2 downto 0);
  signal b_int            : std_logic_vector(MWIDTH-2 downto 0);   
  signal r_int            : std_logic_vector(MWIDTH-2 downto 0);   
  signal by               : std_logic_vector(MWIDTH-1 downto 0); -- B-Y: input to Dcoef multiplier; MWIDTH wide
  signal ry               : std_logic_vector(MWIDTH-1 downto 0); -- R-Y: Multiplier width should define MWIDTH  
  signal y_int_round      : std_logic_vector(OWIDTH+1 downto 0); -- y_int offset compensated and rounded 
  signal y_int_delay      : std_logic_vector(OWIDTH+1 downto 0); -- y_int_offset with delay matching
  signal y_int_postmax    : std_logic_vector(OWIDTH+1 downto 0);
  signal y_int_postmin    : std_logic_vector(OWIDTH+1 downto 0);
  signal cb_int           : std_logic_vector(CWIDTH+MWIDTH-1 downto 0);
  signal cb_int_round     : std_logic_vector(OWIDTH+1 downto 0); 
  signal cb_int_postmax   : std_logic_vector(OWIDTH+1 downto 0);
  signal cb_int_postmin   : std_logic_vector(OWIDTH+1 downto 0);
  signal cr_int           : std_logic_vector(CWIDTH+MWIDTH-1 downto 0);
  signal cr_int_round     : std_logic_vector(OWIDTH+1 downto 0); 
  signal cr_int_postmax   : std_logic_vector(OWIDTH+1 downto 0);
  signal cr_int_postmin   : std_logic_vector(OWIDTH+1 downto 0);
  signal sync_in          : std_logic_vector(2 downto 0); 
  signal sync_out         : std_logic_vector(2 downto 0); 

begin        

---------------------------------------------------------------------
--  Generate the output sync signals  
---------------------------------------------------------------------

  SYNC_in(2) <= PIX_EN_in;
  SYNC_in(1) <= V_SYNC_in;
  SYNC_in(0) <= H_SYNC_in;
  
  del_SYNC : entity work.delay(rtl) 
    generic map ( 
      width => 3, 
      delay => MODULE_LATENCY )   
    port map (
      clk   => clk,
      d     => SYNC_in,  
      q     => SYNC_out,
      ce    => ce);

  PIX_EN_out <= SYNC_out(2);
  V_SYNC_out <= SYNC_out(1);
  H_SYNC_out <= SYNC_out(0);
  
---------------------------------------------------------------------
--  Create Y = a(R-G) + G + b(B-G)  
---------------------------------------------------------------------

  sub_RG : entity work.radd_sub_sclr(rtl)         -- (R - G)
    generic map ( 
      width   => IWIDTH, 
      add     => false,
      fabric  => FABRIC_ADDS,
      a_signed=> false,
      b_signed=> false,
      delay   => ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS))   
    port map (
      clk     => clk,
      a       => G,
      b       => R,
      s       => rg,
      c_in    => logic0,
      ce      => ce,
      sclr    => sclr);   

  sub_BG : entity work.radd_sub_sclr(rtl)         -- (B - G)
    generic map ( 
      width   => IWIDTH, 
      add     => false,
      fabric  => FABRIC_ADDS,
      a_signed=> false,
      b_signed=> false,
      delay   => ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS))   
    port map (
      clk     => clk,
      a       => G,
      b       => B,
      s       => bg,
      c_in    => logic0,
      ce      => ce,
      sclr    => sclr);    

  mult_aRG: entity work.mult(rtl)              -- a * (R - G)
    generic map ( 
      iwidtha => IWIDTH+1, 
      iwidthb => CWIDTH,
      delay   => MULT_DELAY(FAMILY_HAS_MAC))   
    port map (
      clk     => clk,
      ce      => ce,
      sclr    => sclr,
      a       => rg,
      b       => ACOEFvec,
      p       => rgm);  
  sp3_v2_v2p_mult1: if (FAMILY_HAS_MAC=0) generate
     mult_bBG: entity work.mult(rtl)              -- b * (B - G)
      generic map ( 
        iwidtha => IWIDTH+1, 
        iwidthb => CWIDTH,
        delay   => MULT_DELAY(FAMILY_HAS_MAC))   
      port map (
        clk     => clk,
        ce      => ce,
        sclr    => sclr,
        a       => bg,
        b       => BCOEFvec,
        p       => bgm);
    
    add_aRG_bBG : entity work.radd_sub_sclr(rtl)    -- (a * (R - G)) +  (b * (B - G))  :
      generic map ( 
        width => MWIDTH-3, 
        add   => true,
        fabric=> FABRIC_ADDS,
        delay => ADD_DELAY(FAMILY_HAS_MAC, FABRIC_ADDS))   
      port map (
        clk   => clk,
        a     => rgm(IWIDTH+CWIDTH-2 downto IWIDTH+CWIDTH-MWIDTH+2), --  propagate leading MWIDTH-3 bits,
        b     => bgm(IWIDTH+CWIDTH-2 downto IWIDTH+CWIDTH-MWIDTH+2),
        s     => y_inta,
        c_in  => logic0,
        ce    => ce,
        sclr  => sclr);  
  end generate;
  
  v4_mac1: if (FAMILY_HAS_MAC=1) generate  -- DSP48 based implementation
    mult_aCr: entity work.mac(rtl)              -- ACOEFF * Cr + Roffsetvec
      generic map (                                -- offset contains rounding const
        IWIDTHA   => IWIDTH+1, 
        IWIDTHB   => CWIDTH,   
        OWIDTH    => IWIDTH+1+CWIDTH,
        ROUND_MODE=> 0,
        HAS_C     => 1)
      port map (
        clk       => clk,
        ce        => ce,
        sclr      => sclr,
        a         => bg,
        b         => BCOEFvec,
        c         => rgm,
        p         => y_inta_raw);
        
    y_inta <= y_inta_raw(IWIDTH+CWIDTH-1 downto IWIDTH+CWIDTH-MWIDTH+2);