shx.opj

来自「Cadence16.2完全学习手册」· OPJ 代码 · 共 119 行

(ExpressProject "shx"
  (ProjectVersion "19981106")
  (ProjectType "PCB")
  (Folder "Design Resources"
    (Folder "Library")
    (NoModify)
    (File ".\shx.dsn"
      (Type "Schematic Design"))
    (BuildFileAddedOrDeleted "x")
    (CompileFileAddedOrDeleted "x")
    (DRC_Scope "0")
    (DRC_Action "0")
    (DRC_Create_Warnings "FALSE")
    (DRC_Check_Ports "FALSE")
    (DRC_Check_Off-Page_Connectors "FALSE")
    (DRC_Identical_References "TRUE")
    (DRC_Type_Mismatch "TRUE")
    (DRC_Report_Ports_and_Off-page_Connectors "FALSE")
    (DRC_SDT_Compatibility "FALSE")
    (DRC_Report_Off-grid_Objects "FALSE")
    (DRC_Check_Unconnected_Nets "TRUE")
    (DRC_Check_for_Misleading_TAP "FALSE")
    (DRC_Visible_Power_pins "FALSE")
    (DRC_Report_Netnames "FALSE")
    (DRC_View_Output "FALSE")
    (DRC_Report_File
       "C:\Documents and Settings\Administrator\桌面\XWJ时小霞\aaa.DRC")
    (ANNOTATE_Scope "0")
    (ANNOTATE_Mode "1")
    (ANNOTATE_Action "0")
    (Annotate_Page_Order "0")
    (ANNOTATE_Reset_References_to_1 "FALSE")
    (ANNOTATE_No_Page_Number_Change "FALSE")
    (ANNOTATE_Property_Combine "{Value}{Source Package}{POWER_GROUP}")
    (ANNOTATE_IncludeNonPrimitive "FALSE")
    (ANNOTATE_Refdes_Control_Required "FALSE")
    (FLDSTUFF_Scope "0")
    (FLDSTUFF_Action "0")
    (FLDSTUFF_Report_File ".\shx.RPT")
    (FLDSTUFF_Update_File ".\shx.UPD")
    (FLDSTUFF__Uppercase_Result_Property "FALSE")
    (FLDSTUFF_Uppercase_Update_Property "FALSE")
    (FLDSTUFF_Uppercase_Unconditionally "FALSE")
    (FLDSTUFF_Visibility "0")
    (FLDSTUFF_inst_or_occurrence "0")
    (FLDSTUFF_Create_Report_File "FALSE")
    (Board_sim_option "VHDL_flow")
    ("Create Allegro Netlist" "TRUE")
    ("Allegro Netlist Directory"
       "C:\DOCUMENTS AND SETTINGS\ADMINISTRATOR\桌面\XWJ时小霞\ALLEGRO")
    ("View Allegro Netlist Files" "FALSE")
    ("Update Allegro Board" "FALSE")
    ("Allegro Netlist Output Board File" "allegro\shx.brd")
    ("Allegro Netlist Remove Etch" "FALSE")
    ("Allegro Netlist Place Changed Component" "ALWAYS_REPLACE")
    ("Allegro Netlist Open Board in Allegro" "ALLEGRO")
    ("Allegro Setup Configuration File"
       "C:\Cadence\SPB_16.2\tools\capture\allegro.cfg")
    ("Allegro Setup Backup Versions" "3")
    ("Allegro Netlist Combine Property String" "PCB Footprint")
    ("Allegro Netlist Ignore Fixed Property" "FALSE")
    ("Allegro Netlist User Defined Property" "FALSE")
    (Netlist_TAB "0")
    (GATE_&_PIN_SWAP_Scope "0")
    (GATE_&_PIN_SWAP_File_Name "E:\CADENCE资料\DSP CIS\SHX.SWP")
    (Backannotation_TAB "0")
    (Annotate_type "Default")
    (width_pages "100")
    (width_start "80")
    (width_End "80"))
  (Folder "Outputs"
    (File ".\aaa.drc"
      (Type "Report"))
    (File ".\allegro\pstxnet.dat"
      (Type "Report")
      (DisplayName "pstxnet.dat"))
    (File ".\allegro\pstxprt.dat"
      (Type "Report")
      (DisplayName "pstxprt.dat"))
    (File ".\allegro\pstchip.dat"
      (Type "Report")
      (DisplayName "pstchip.dat")))
  (Folder "Referenced Projects")
  (PartMRUSelector
    (TitleBlock0
      (LibraryName "E:\CADENCE\SPB_16.0\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB")
      (DeviceIndex "0")))
  (GlobalState
    (FileView
      (Path "Design Resources")
      (Path "Design Resources"
         "C:\Documents and Settings\dudu\桌面\17章\17\17.1.2-17.1.3 原理图的绘制与完善\shx.dsn")
      (Path "Design Resources"
         "C:\Documents and Settings\dudu\桌面\17章\17\17.1.2-17.1.3 原理图的绘制与完善\shx.dsn"
         "SCHEMATIC1")
      (Path "Outputs")
      (Select "Design Resources"
         "C:\Documents and Settings\dudu\桌面\17章\17\17.1.2-17.1.3 原理图的绘制与完善\shx.dsn"
         "SCHEMATIC1" "PAGE1"))
    (HierarchyView)
    (Doc
      (Type "COrCapturePMDoc")
      (Frame
        (Placement "44 0 1 -1 -1 -4 -30 0 200 0 364"))
      (Tab 0))
    (Doc
      (Type "COrSchematicDoc")
      (Frame
        (Placement "44 2 3 -1 -1 -4 -30 44 936 58 486")
        (Scroll "0 0")
        (Zoom "100")
        (Occurrence "/"))
      (Path
         "C:\DOCUMENTS AND SETTINGS\DUDU\桌面\17章\17\17.1.2-17.1.3 原理图的绘制与完善\SHX.DSN")
      (Schematic "SCHEMATIC1")
      (Page "PAGE1")))
  (MPSSessionName "dudu")
  (ISPCBBASICLICENSE "false"))