specctra.did

Cadence16.2完全学习手册

rule class '_difpr_DP-D1' (neck_down_width 6)
rule class '_difpr_DP-BA' (diffpair_line_width 6)
rule class '_difpr_DP-BA' (neck_down_width 6)
rule class _difpr_DP1 (diffpair_line_width 6)
rule class _difpr_DP1 (neck_down_width 6)
rule class '_difpr_DP-BD' (diffpair_line_width 6)
rule class '_difpr_DP-BD' (neck_down_width 6)
rule class '_difpr_DP-RA' (diffpair_line_width 6)
rule class '_difpr_DP-RA' (neck_down_width 6)
rule class '_difpr_DP-RD' (diffpair_line_width 6)
rule class '_difpr_DP-RD' (neck_down_width 6)
rule class '_difpr_DP-VD' (diffpair_line_width 6)
rule class '_difpr_DP-VD' (neck_down_width 6)
rule class '_difpr_DP-BD1' (diffpair_line_width 6)
rule class '_difpr_DP-BD1' (neck_down_width 6)
rule class '_difpr_DP-A' (diffpair_line_width 6)
rule class '_difpr_DP-A' (neck_down_width 6)
rule class '_difpr_DP-RA1' (diffpair_line_width 6)
rule class '_difpr_DP-RA1' (neck_down_width 6)
rule class '_difpr_DP-D' (diffpair_line_width 6)
rule class '_difpr_DP-D' (neck_down_width 6)
rule class '_difpr_DP-Q' (diffpair_line_width 6)
rule class '_difpr_DP-Q' (neck_down_width 6)
rule class '_difpr_DP-RCS' (diffpair_line_width 6)
rule class '_difpr_DP-RCS' (neck_down_width 6)
rule class '_difpr_DP-A1' (diffpair_line_width 6)
rule class '_difpr_DP-A1' (neck_down_width 6)
rule class '_difpr_DP-A2' (diffpair_line_width 6)
rule class '_difpr_DP-A2' (neck_down_width 6)
write colormap _notify.std
# do C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/#Taaaaab00584.tmp
unselect all routing
select component U9
select component U8
select component U7
select component U5
select component U4
select component U22
select component U19
select component U21
select component U18
select component U17
select component U16
select component U15
select component U14
select component U13
select component U12
select component U11
select component U10
select component R5
select component R18
select component R17
select component R16
select component R15
select component R14
select component R9
select component R8
select component R7
select component R6
select component R13
select component R12
select component R11
select component R10
select component R4
select component R3
select component R2
select component R1
select component L6
select component L5
select component L4
select component L3
select component L2
select component L1
select component J3
select component J2
select component J1
select component D4
select component D3
select component D2
select component D1
select component C6
select component C5
select component C27
select component C26
select component C24
select component C23
select component C9
select component C8
select component C7
select component C14
select component C13
select component C12
select component C11
select component C10
select component C4
select component C3
select component C28
select component C25
select component C22
select component C21
select component C20
select component C2
select component C19
select component C18
select component C17
select component C16
select component C15
select component C1
select component U23
select component U20
select component U3
select component U2
select component U1
select component U6
select net VCC
select net GND
select net RA14
select net RA10
select net RD1
select net DCLK
select net RA12
select net RD4
select net RA13
select net RA4
select net RA15
select net RD7
select net RD0
select net RA8
select net RD3
select net RA5
select net N17076
select net RD6
select net A23
select net RA9
select net A22
select net RA11
select net A21
select net N17072
select net RA1
select net A20
select net N16756
select net RA0
select net A19
select net BNC3
select net A18
select net GND_EARTH
select net A17
select net BNC2
select net A16
select net N17068
select net RCS1
select net A15
select net OUTA
select net A14
select net N16748
select net WSTAT
select net A13
select net N17064
select net VCLKA
select net A12
select net N17060
select net RCS0
select net A11
select net RCS2
select net A10
select net RCS3
select net A9
select net N17056
select net NCS
select net A8
select net N16740
select net GAIN
select net A7
select net OUTB
select net A6
select net RWE
select net A5
select net OE
select net A4
select net Q2
select net A3
select net VCLKC
select net Q7
select net A2
select net DATA
select net Q6
select net A1
select net Q4
select net A0
select net Q5
select net Q0
select net Q1
select net Q3
select net D8
select net V12P
select net AGND
select net D12
select net V12N
select net BA7
select net D11
select net BA6
select net D1
select net BA5
select net BA4
select net BA3
select net D13
select net BA2
select net D14
select net BA1
select net D15
select net BA0
select net D3
select net BD15
select net D4
select net BD14
select net D2
select net BD13
select net D5
select net BD12
select net D9
select net BD11
select net BD10
select net D10
select net BD9
select net BD8
select net D0
select net BD7
select net D6
select net BD6
select net D7
select net BD5
select net BD4
select net N17361
select net BD3
select net BD2
select net N17197
select net BD1
select net N17221
select net BD0
select net N17281
select net N17269
select net N17341
select net DHEN
select net DEN
select net MWR
select net MRD
select net RDY
select net DDIR
select net AEN
select net WAIT
select net N17361_4621
select net MCLK
select net N17197_4623
select net RESET
select net N17221_4624
select net BWR
select net BRESET
select net N17281_4627
select net BRD
select net SEL
select net N17269_4629
select net FPGA
select net HS
select net N17341_4632
select net N30149
select net N30003
select net VREF
select net N29863
select net N29715
select net VD7
select net VD6
select net VD5
select net VD4
select net VD3
select net VD2
select net VD1
select net VD0
select net N407439
select net N17052
select net N16732
select net N17048
select net N17044
select net GND_POWER
select net N17104
select net N17100
select net N17096
select net N17092
select net RA3
select net RA2
select net RD2
select net N17088
select net RA7
select net N17084
select net RD5
select net N17080
select net RA6
set route_diagonal 0
grid wire 0.010000 (direction x) (offset 0.000000)
grid wire 0.010000 (direction y) (offset 0.000000)
grid via 0.010000 (direction x) (offset 0.000000)
grid via 0.010000 (direction y) (offset 0.000000)
protect all wires
direction TOP horizontal
select layer TOP
unprotect layer_wires TOP
direction BOTTOM vertical
select layer BOTTOM
unprotect layer_wires BOTTOM
cost via -1
set turbo_stagger off
limit outside -1
rule pcb (patterns_allowed  trombone accordion)
set pattern_stacking on
rule pcb (sawtooth_amplitude -1 -1)
rule pcb (sawtooth_gap -1)
rule pcb (accordion_amplitude -1 -1)
rule pcb (accordion_gap -1)
rule pcb (trombone_run_length -1)
rule pcb (trombone_gap -1)
unprotect selected
filter 2
center
miter 4 (style diagonal) (pin) (slant) (tjunction) (bend) (layer TOP BOTTOM)
delete conflicts (include fast)
write routes (changed_only) (reset_changed) C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/#Taaaaac00584.tmp
quit -c