specctra.log,3

Cadence16.2完全学习手册

# 
# ===============================================================================
#                               Allegro PCB Router                               
# Copyright 1990-2006 Cadence Design Systems, Inc.  All Rights Reserved.
# ===============================================================================
# 
# Software licensed for sale by Cadence Design Systems, Inc.
# Current time = Mon May 04 11:22:24 2009
# 
# Allegro PCB Router v16-2-57 made 2008/10/14 at 13:29:47
# Running on: pc-20090426gjon, OS Version: WindowsNT 5.1.2600, Architecture: Intel Pentium
# Licensing: The program will not obey any unlicensed rules
# No graphics will be displayed.
# Design Name F:/wenjian/第十一章/自动布线\Autorouted.dsn
# Batch File Name: pasde.do
# Did File Name: F:/wenjian/第十一章/自动布线/specctra.did
# Current time = Mon May 04 11:22:25 2009
# PCB F:/wenjian/第十一章/自动布线
# Master Unit set up as: MIL 1000
# PCB Limits xlo=-1192.5000 ylo=-590.0000 xhi=4142.5000 yhi=4470.0000
# Total 69 Images Consolidated.
# Via VIA z=1, 2 xlo=-12.0000 ylo=-12.0000 xhi= 12.0000 yhi= 12.0000
# 
#    VIA     TOP  BOTTOM
# 
#    TOP  ------   VIA  
# BOTTOM   VIA    ------
# 
# Wires Processed 324, Vias Processed 26
# Using colormap in design file.
# Layers Processed: Signal Layers 2
# Layers Processed: Power Layers 2
# Components Placed 85, Images Processed 100, Padstacks Processed 13
# Nets Processed 182, Net Terminals 798
# PCB Area=21340000.000  EIC=59  Area/EIC=361694.915  SMDs=65
# Total Pin Count: 839
# Signal Connections Created 188
# 
# Design Rules --------------------------------------------
# Via Grid 0.0100 with offset 0.0000
# Layer TOP Horz Signal Wire Grid 0.0100 with offset 0.0000, Width= 6.0000, Clearance= 6.0000
# Layer BOTTOM Vert Signal Wire Grid 0.0100 with offset 0.0000, Width= 6.0000, Clearance= 6.0000
# Cpu Time = 0:00:00  Elapsed Time = 0:00:00
# 
# Wiring Statistics ----------------- F:/wenjian/第十一章/自动布线\Autorouted.dsn
# Nets 182 Connections 572 Unroutes 327
# Signal Layers 2 Power Layers 2
# Wire Junctions 74, at vias 21 Total Vias 26
# Percent Connected   41.08
# Manhattan Length 353784.8200 Horizontal 167757.8470 Vertical 186026.9730
# Routed Length 173423.4054 Horizontal 76412.4600 Vertical 110645.9800
# Ratio Actual / Manhattan   0.4902
# Unconnected Length 181275.6600 Horizontal 88839.4500 Vertical 92436.2100
# Total Conflicts: 20 (Cross: 0, Clear: 20, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Cpu Time = 0:00:00  Elapsed Time = 0:00:02
# Loading Do File pasde.do ...
# Loading Do File F:/wenjian/第十一章/自动布线\Autorouted_rules.do ...
# Nets VD0 and VD3 have been defined as a balanced pair.
# Nets RD3 and RD0 have been defined as a balanced pair.
# Nets RA3 and RA0 have been defined as a balanced pair.
# Nets BD0 and BD3 have been defined as a balanced pair.
# Nets N16740 and N16748 have been defined as a balanced pair.
# Nets BA0 and BA3 have been defined as a balanced pair.
# Nets D10 and D13 have been defined as a balanced pair.
# Nets A20 and A23 have been defined as a balanced pair.
# Nets A10 and A13 have been defined as a balanced pair.
# <<WARNING:>> Could not form pair of nets RCS3 and RCS0.
# <<WARNING:>> Could not form pair of nets Q3 and Q0.
# Nets D0 and D3 have been defined as a balanced pair.
# Nets RA13 and RA10 have been defined as a balanced pair.
# Nets A0 and A3 have been defined as a balanced pair.
# Nets BD10 and BD13 have been defined as a balanced pair.
# Colormap Written to File _notify.std
# Enter command <# Loading Do File C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/#Taaaaab02804.tmp ...
# All Components Unselected.
# All Nets Unselected.
set route_diagonal 4
grid wire 0.010000 (direction x) (offset 0.000000)
grid wire 0.010000 (direction y) (offset 0.000000)
grid via 0.010000 (direction x) (offset 0.000000)
grid via 0.010000 (direction y) (offset 0.000000)
protect all wires
# All Wires Protected.
direction TOP horizontal
select layer TOP
unprotect layer_wires TOP
# Wires on layer TOP were Unprotected.
direction BOTTOM vertical
select layer BOTTOM
unprotect layer_wires BOTTOM
# Wires on layer BOTTOM were Unprotected.
cost via 100
set turbo_stagger on
limit outside 32.000000
rule pcb (patterns_allowed  trombone accordion)
set pattern_stacking on
rule pcb (sawtooth_amplitude -1 -1)
rule pcb (sawtooth_gap -1)
rule pcb (accordion_amplitude -1 -1)
rule pcb (accordion_gap -1)
rule pcb (trombone_run_length -1)
rule pcb (trombone_gap -1)
smart_route (min_via_grid 0.010000) (min_wire_grid 0.010000) (auto_fanout on) (auto_fanout_via_share on) (auto_fanout_pin_share on) (auto_testpoint off) (auto_miter on)
# Smart Route: Executing bus diagonal.
# Diagonal wire corners are preferred.
# Current time = Mon May 04 11:23:09 2009
# 
#    VIA     TOP  BOTTOM
# 
#    TOP  ------   VIA  
# BOTTOM   VIA    ------
# 
# 
# Design Rules --------------------------------------------
# Via Grid 0.0100 with offset 0.0000
# Layer TOP Horz Signal Wire Grid 0.0100 with offset 0.0000, Width= 6.0000, Clearance= 6.0000
# Layer BOTTOM Vert Signal Wire Grid 0.0100 with offset 0.0000, Width= 6.0000, Clearance= 6.0000
# 
# Wiring Statistics ----------------- F:/wenjian/第十一章/自动布线\Autorouted.dsn
# Nets 182 Connections 572 Unroutes 326
# Signal Layers 2 Power Layers 2
# Wire Junctions 73, at vias 21 Total Vias 26
# Percent Connected   41.26
# Manhattan Length 351864.4000 Horizontal 167252.7020 Vertical 184611.6980
# Routed Length 173423.4054 Horizontal 76412.4600 Vertical 110645.9800
# Ratio Actual / Manhattan   0.4929
# Unconnected Length 180579.6800 Horizontal 87868.2300 Vertical 92711.4500
# Attempts 111 Successes 7 Failures 104 Vias 26
# 90 degree wire corners are preferred.
# Total Conflicts: 20 (Cross: 0, Clear: 20, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Cpu Time = 0:00:00  Elapsed Time = 0:00:00
# 
# Wiring Statistics ----------------- F:/wenjian/第十一章/自动布线\Autorouted.dsn
# Nets 182 Connections 572 Unroutes 319
# Signal Layers 2 Power Layers 2
# Wire Junctions 73, at vias 21 Total Vias 26
# Percent Connected   42.48
# Manhattan Length 351864.4000 Horizontal 167252.7020 Vertical 184611.6980
# Routed Length 177050.4563 Horizontal 76706.4600 Vertical 114145.9800
# Ratio Actual / Manhattan   0.5032
# Unconnected Length 177079.6800 Horizontal 87868.2300 Vertical 89211.4500
# <<WARNING:>> Smart Route: 93.69 percent of bus attempts failed.
# 90 degree wire corners are preferred.
# Smart Route: Executing 25 route passes.
# Current time = Mon May 04 11:23:10 2009
# 
#    VIA     TOP  BOTTOM
# 
#    TOP  ------   VIA  
# BOTTOM   VIA    ------
# 
# 
# Design Rules --------------------------------------------
# Via Grid 0.0100 with offset 0.0000
# Layer TOP Horz Signal Wire Grid 0.0100 with offset 0.0000, Width= 6.0000, Clearance= 6.0000
# Layer BOTTOM Vert Signal Wire Grid 0.0100 with offset 0.0000, Width= 6.0000, Clearance= 6.0000
# 
# Wiring Statistics ----------------- F:/wenjian/第十一章/自动布线\Autorouted.dsn
# Nets 182 Connections 572 Unroutes 319
# Signal Layers 2 Power Layers 2
# Wire Junctions 73, at vias 21 Total Vias 26
# Percent Connected   42.48
# Manhattan Length 351864.4000 Horizontal 167252.7020 Vertical 184611.6980
# Routed Length 177050.4563 Horizontal 76706.4600 Vertical 114145.9800
# Ratio Actual / Manhattan   0.5032
# Unconnected Length 177079.6800 Horizontal 87868.2300 Vertical 89211.4500
# 3 bend points have been removed.
# Attempts 414 Successes 1 Failures 416 Vias 25
# 0 bend points have been removed.
# Attempts 414 Successes 0 Failures 417 Vias 25
# 0 bend points have been removed.
# 0 bend points have been removed.
# 1 bend points have been removed.
# Start Route Pass 1 of 25
# Routing 635 wires.
# 32 bend points have been removed.
# 31 bend points have been removed.
# Total Conflicts: 489 (Cross: 400, Clear: 89, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 236
# Attempts 598 Successes 285 Failures 313 Vias 24
# Cpu Time = 0:00:02  Elapsed Time = 0:00:03
# End Pass 1 of 25
# Wiring Written to File F:/wenjian/第十一章/自动布线\bestsave.w
# <<WARNING:>> Smart Route: Unroute count 236 is very high after 1 passes. 
# Design may not reach 100%. 
# Check placement, components outside boundary, design rules, keepout positions
# Start Route Pass 2 of 25
# Routing 669 wires.
# 36 bend points have been removed.
# 35 bend points have been removed.
# Total Conflicts: 1070 (Cross: 711, Clear: 359, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 200
# Attempts 623 Successes 326 Failures 297 Vias 31
# Cpu Time = 0:00:05  Elapsed Time = 0:00:05
# Conflict Reduction -1.1881
# End Pass 2 of 25
# <<WARNING:>> Smart Route: Conflict reduction rate 0 is very low 
# after 2 passes. 
# Design may not reach 100%. 
# Check number of layers, grids and design rules.
# Start Route Pass 3 of 25
# Routing 682 wires.
# 41 bend points have been removed.
# 46 bend points have been removed.
# Total Conflicts: 1019 (Cross: 707, Clear: 312, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 196
# Attempts 633 Successes 325 Failures 308 Vias 34
# Cpu Time = 0:00:07  Elapsed Time = 0:00:07
# Conflict Reduction  0.0477
# End Pass 3 of 25
# <<WARNING:>> Smart Route: Average reduction ratio only 2 after 3 passes. 
# Design may converge very slowly. 
# Monitor status file carefully.
# Start Route Pass 4 of 25
# Routing 686 wires.
# 46 bend points have been removed.
# 25 bend points have been removed.
# Total Conflicts: 1032 (Cross: 767, Clear: 265, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 186
# Attempts 625 Successes 383 Failures 242 Vias 28
# Cpu Time = 0:00:08  Elapsed Time = 0:00:08
# Conflict Reduction -0.0128
# End Pass 4 of 25
# <<WARNING:>> Smart Route: Average reduction ratio only 1 after 4 passes. 
# Design may converge very slowly. 
# Monitor status file carefully.
# Start Route Pass 5 of 25
# Routing 693 wires.
# 31 bend points have been removed.
# 14 bend points have been removed.
# Total Conflicts: 1041 (Cross: 774, Clear: 267, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 183
# Attempts 640 Successes 407 Failures 233 Vias 28
# Cpu Time = 0:00:05  Elapsed Time = 0:00:06
# Conflict Reduction -0.0087
# End Pass 5 of 25
# 0 bend points have been removed.
# 0 bend points have been removed.
# <<WARNING:>> Smart Route: Average reduction ratio only 1 after 5 passes. 
# Design may converge very slowly. 
# Monitor status file carefully.
# Start Route Pass 6 of 25
# Routing 590 wires.
# 1 bend points have been removed.
# 11 bend points have been removed.
# Total Conflicts: 565 (Cross: 523, Clear: 42, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 214
# Attempts 535 Successes 331 Failures 204 Vias 28
# Cpu Time = 0:00:07  Elapsed Time = 0:00:07
# End Pass 6 of 25
# Smart Route: Smart_route progressing normally after 6 passes.
# Start Route Pass 7 of 25
# Routing 538 wires.
# 10 bend points have been removed.
# 9 bend points have been removed.
# Total Conflicts: 637 (Cross: 581, Clear: 56, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 208
# Attempts 498 Successes 298 Failures 200 Vias 26
# Cpu Time = 0:00:06  Elapsed Time = 0:00:07
# End Pass 7 of 25
# Smart Route: Smart_route progressing normally after 7 passes.
# Start Route Pass 8 of 25
# Routing 582 wires.
# 12 bend points have been removed.
# 8 bend points have been removed.
# Total Conflicts: 533 (Cross: 432, Clear: 101, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 213
# Attempts 539 Successes 322 Failures 217 Vias 29
# Cpu Time = 0:00:08  Elapsed Time = 0:00:08
# End Pass 8 of 25
# Wiring Written to File F:/wenjian/第十一章/自动布线\bestsave.w
# Smart Route: Smart_route progressing normally after 8 passes.
# Start Route Pass 9 of 25
# Routing 512 wires.
# 9 bend points have been removed.
# 10 bend points have been removed.
# Total Conflicts: 517 (Cross: 434, Clear: 83, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 210
# Attempts 473 Successes 255 Failures 218 Vias 29
# Cpu Time = 0:00:07  Elapsed Time = 0:00:08
# End Pass 9 of 25
# Wiring Written to File F:/wenjian/第十一章/自动布线\bestsave.w
# Smart Route: Smart_route progressing normally after 9 passes.
# Start Route Pass 10 of 25
# Routing 531 wires.
# 17 bend points have been removed.
# 6 bend points have been removed.
# Total Conflicts: 741 (Cross: 579, Clear: 162, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 195
# Attempts 492 Successes 271 Failures 221 Vias 31
# Cpu Time = 0:00:08  Elapsed Time = 0:00:09
# End Pass 10 of 25
# Smart Route: Smart_route progressing normally after 10 passes.
# Start Route Pass 11 of 25
# Routing 525 wires.
# 1 bend points have been removed.
# 7 bend points have been removed.
# Total Conflicts: 352 (Cross: 319, Clear: 33, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 220
# Attempts 312 Successes 271 Failures 41 Vias 32
# Cpu Time = 0:00:03  Elapsed Time = 0:00:03
# End Pass 11 of 25
# Wiring Written to File F:/wenjian/第十一章/自动布线\bestsave.w
# Smart Route: Smart_route progressing normally after 11 passes.
# Start Route Pass 12 of 25
# Routing 506 wires.
# 4 bend points have been removed.
# 3 bend points have been removed.
# Total Conflicts: 333 (Cross: 293, Clear: 40, Xtalk: 0, Length: 0, Polygon Clear: 0 )
# Total Unroutes: 224
# Attempts 303 Successes 255 Failures 48 Vias 32
# Cpu Time = 0:00:03  Elapsed Time = 0:00:03
# End Pass 12 of 25
# Wiring Written to File F:/wenjian/第十一章/自动布线\bestsave.w
# Smart Route: Smart_route progressing normally after 12 passes.
# Start Route Pass 13 of 25
# Routing 467 wires.
# 13 bend points have been removed.
# 12 bend points have been removed.