videocomposer.vhd

&#65279 The purpose of this lab is to introduce the concept of FSMs with a datapath, and to stud

USE WORK.ALL;
USE WORK.package_microassemblycode.all;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
entity videocomposer is
    generic(
        size: integer;
        asize:integer);
    port(
         clk : in std_logic;
         reset: in std_logic;
         datain: in std_logic_vector(size*3-1 downto 0);
         datainready: in std_logic;
         datainread : out std_logic;
         dataout : out std_logic_vector(size*3-1 downto 0);
         dataoutready : out std_logic;
         dataoutread : in std_logic);
     end videocomposer;
     
architecture composite of videocomposer is
      signal red_in : std_logic_vector(size-1 downto 0);
      signal green_in : std_logic_vector(size-1 downto 0);
      signal blue_in : std_logic_vector(size-1 downto 0);
      TYPE State_Type IS (S_ReadGreenWriteRed,S_ReadRed,reset_state,S_ResetR0, S_ReadBlueWriteGreen,S_ProcessBlue, S_WriteBlue, S_Idle);
      signal datapath_inport : std_logic_vector(size-1 downto 0);
      signal datapath_outport : std_logic_vector(size-1 downto 0);
      signal red_out : std_logic_vector(size-1 downto 0);
      signal green_out : std_logic_vector(size-1 downto 0);
      signal blue_out : std_logic_vector(size-1 downto 0);
      signal inst : Instruction_Type:=('0',Rx,Rx,Rx,OpAnd,OpPass,'0');
      signal current_state,next_state: state_type;
      signal current_counter:integer :=0;
      signal next_counter:integer :=0;
      
      constant MEM : program_type :=(
--IE  W  RA RB  alu  shifter OE    count
('1',R1,R0,R0,OpAnd,OpPass,'0'),--0 ReadRed => -- ROM Instr 0
('0',R0,R1,R1,OpXor,OpPass,'0'),--1 Reset R0=0
('1',R2,R1,R0,OpAdd,OpPass,'1'),--2 ReadGreenWriteRed => -- ROM Instr 1
('1',R3,R2,R0,OpAdd,OpPass,'1'),--3 ReadBlueWriteGreen => -- ROM Instr 2

('0',R3,R3,R0,OpAdd,OpRotL,'0'),--4 ProcessBlue => -- ROM Instr 4-8 
                                 --1st rotate left
('0',R3,R3,R0,OpAdd,OpRotL,'0'),--5 2nd rotate left 
('0',R4,R0,R0,OpInc,OpRotL,'0'),--6 mask1=00000010              
('0',R4,R4,R0,OpInc,OpPass,'0'),--7 mask1=00000011

('0',R6,R3,R4,OpAnd,OpPass,'0'),--8 tmp=B' and mask1
('0',R0,R6,R0,OpAdd,OpPass,'1'),--9 tmp-->outport judge 
('0',R0,R3,R0,OpAdd,OpPass,'1'),--10 outport='00000000',so out R3
    
('0',R0,R0,R0,Opdec,OpPass,'1'),--11 outport/='00000000',so out '11111111'
                                --saturate
('0',Rx,Rx,Rx,OpAnd,OpPass,'0'), --12-NULL OPERATION
('0',Rx,Rx,Rx,OpAnd,OpPass,'0'), --13-NULL OPERATION
('0',Rx,Rx,Rx,OpAnd,OpPass,'0'), --14-NULL OPERATION
('0',R0,R0,R0,OpXor,OpPass,'0')  --15-NULL OPERATION
);

      
      
      component dataPath IS
           GENERIC (
                 Size  : INTEGER := 8; -- # bits in word
                 ASize : INTEGER := 3  -- # bits in address
                   );
           PORT (
                 InPort      : IN  STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
                 OutPort     : OUT STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
                 Clk         : IN  STD_LOGIC;
                 Instr       : IN Instruction_type);-- :=( '0' , Rx   , Rx   , Rx   , OpAnd   , OpAnd     , '0' ));
           END component;
         
      begin
          inst <= mem(current_counter);
          red_in<= DataIn(Size*3-1 downto Size*3-Size*1);
          green_in<=DataIn(Size*3-1-Size downto Size*3-Size*2);
          blue_in<=DataIn(Size*3-1-size*2 downto Size*3-Size*3);
            
         process(current_state,current_counter,datapath_outport)
             
            begin
                datainread<='0';---------
               case current_state is
                 when reset_state => 
                     dataoutready<='0';
                     --ASSERT false
                     --report "0000reset state!!!"
                     --severity note;
                     if datainready='1' then
                        next_state<=S_ReadRed;
         							   next_counter <= 0;
         							else 
         							   next_state<=S_Idle;
         							   next_counter<=15;
  							end if;
                         
                 when S_ReadRed => -- ROM Instr 0
                     --ASSERT false
                     --report "1111readred state!!!"
                     --severity note;
                     datapath_inport<= red_in;
                     next_state<=S_ResetR0;--S_ReadGreenWriteRed;
                     next_counter<=1;
                     --datainread<='0';
                 when S_ResetR0 => -- RESET R0=0
                     next_state<=S_ReadGreenWriteRed;
                     next_counter<=2;
                     datainread<='1';---readed i can begin output
                 when S_ReadGreenWriteRed => -- ROM Instr 2
                     datapath_inport<=green_in;
                     red_out <= datapath_outport;
                     next_counter <= 3;
         							next_state <= S_ReadBlueWriteGreen;
                 when S_ReadBlueWriteGreen => -- ROM Instr 3
                     datapath_inport<=blue_in;
                     green_out <= datapath_outport;
                     next_counter <= 4;
         							next_state <= S_ProcessBlue;
         							--datainread<='1';-------it's not critical...tb still wait the output enable signal
                 when S_ProcessBlue => -- ROM Instr 4-8
                     --ASSERT false
                     --report "8888processblue state!!!"
                     --severity note;
                     IF current_counter < 9 THEN
                        next_counter <= current_counter + 1;
                        next_state <= S_ProcessBlue;
                     ELSE
                        IF datapath_outport = "00000000" THEN
                           next_counter <= 10;
                        ELSE
                           next_counter <= 11;
                        END IF;
                        next_state <= S_WriteBlue;
                     END IF;
                     --dataoutready<='0';
         
                 when S_WriteBlue => -- ROM Instr 10 or 11
                       			blue_out <= datapath_outport;
                          dataoutready<='1'; --------------                     
                       			next_state <= S_Idle;
                       			next_counter<=15;
                       			datainread<='1';
                 when S_Idle =>
                     dataoutready<='0';
                     
                     if (datainready='1') then
                         next_state<=S_ReadRed;
            								 next_counter<=0; 
                     else 
                         next_state<=S_Idle;next_counter<=15;
                     end if;
                       			
                 when OTHERS =>
                     ASSERT false
                     report "illegal FSM state, testbench error"
                     severity error;
            END CASE;

                 
        end process;
         DataOut(Size*3-1 downto Size*3-Size*1) <=red_out;--green_out;--blue_out;--red_out;
         DataOut(Size*3-1-Size downto Size*3-Size*2) <= green_out;--blue_out;--red_out;--green_out;
         DataOut(Size*3-1-size*2 downto Size*3-Size*3) <= blue_out;--red_out;--green_out;--blue_out;
         
        process(Clk,reset)
           begin
              if(reset='0') then
                  current_state<=reset_state;
                  current_counter<=0;
                             
              elsif Clk'event and Clk='1' then
                  current_state<=next_state;
                  current_counter<= next_counter;
                            
              end if;
        end process;
 
    u1: datapath generic map(size,asize) 
        port map ( datapath_inport,datapath_outport,clk,inst);
         
end composite;