selector.vhd

&#65279 The purpose of this lab is to introduce the concept of FSMs with a datapath, and to stud

USE WORK.ALL;

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY selector IS
  GENERIC (
    Size: INTEGER
  );
  PORT (
    A     : IN  STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
    B     : IN  STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
    Ctrl  : IN  STD_LOGIC;

    Q     : OUT STD_LOGIC_VECTOR(Size-1 DOWNTO 0)
  );
END selector;

ARCHITECTURE behaviour OF selector IS

BEGIN

  PROCESS(A,B,Ctrl)

  BEGIN

    CASE Ctrl IS
      WHEN '1' => Q <= A;
      WHEN '0' => Q <= B;

      WHEN OTHERS => ASSERT FALSE REPORT"Ctrl out of range, testbench error" SEVERITY ERROR;
    END CASE;

  END PROCESS;
END behaviour;