_info

&#65279 The purpose of this lab is to introduce the concept of FSMs with a datapath, and to stud

m255
13
cModel Technology
dH:\MODELSIM\VHDL-Lab4
Ealu
w1127037318
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
FH:/MODELSIM/VHDL-Lab4/alu.vhd
l0
L7
V4i;HEQ3XSY@>GK[m?i[]F3
OV;C;6.0c;29
32
o-work DATAPATH_LIB -O0
tExplicit 1 GenerateLoopIterationMax 100000
Abehaviour
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work alu 4i;HEQ3XSY@>GK[m?i[]F3
l23
L21
VL3g>^EdLiTQChK=YUcz7P3
OV;C;6.0c;29
32
M2 ieee std_logic_1164
M1 ieee std_logic_arith
o-work DATAPATH_LIB -O0
tExplicit 1 GenerateLoopIterationMax 100000
Edatapath
w1127037318
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DP work package_microassemblycode clWHE8X0I:Wk68Q8FGJbM3
FH:/MODELSIM/VHDL-Lab4/dataPath.vhd
l0
L7
V?TO]6jT]a9d>D]cNcGi7B1
OV;C;6.0c;29
32
o-work DATAPATH_LIB -O0
tExplicit 1 GenerateLoopIterationMax 100000
Abehaviour
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DP work package_microassemblycode clWHE8X0I:Wk68Q8FGJbM3
DE work datapath ?TO]6jT]a9d>D]cNcGi7B1
l107
L21
VQm5oig3D4FhnijZj[N[=F2
OV;C;6.0c;29
32
M2 work package_microassemblycode
M1 ieee std_logic_1164
o-work DATAPATH_LIB -O0
tExplicit 1 GenerateLoopIterationMax 100000
Ppackage_microassemblycode
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OE;C;6.0;29
32
M1 ieee std_logic_1164
w1127037318
FH:/MODELSIM/VHDL-Lab4/package_microAssemblyCode.vhd
l0
L6
VclWHE8X0I:Wk68Q8FGJbM3
OV;C;6.0c;29
o-work DATAPATH_LIB -O0
tExplicit 1 GenerateLoopIterationMax 100000
Eregfile
w1127037318
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_signed <9<Kcl:S52:oW`F]FQhb20
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
FH:/MODELSIM/VHDL-Lab4/regFile.vhd
l0
L8
VVg?b5I[S69QQ[B0o9OAQa1
OV;C;6.0c;29
32
o-work DATAPATH_LIB -O0
tExplicit 1 GenerateLoopIterationMax 100000
Abehaviour
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_signed <9<Kcl:S52:oW`F]FQhb20
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work regfile Vg?b5I[S69QQ[B0o9OAQa1
l39
L32
VaBTTQf?Bojcz1lhaGl>ZQ0
OV;C;6.0c;29
32
M3 ieee std_logic_1164
M2 ieee std_logic_signed
M1 ieee std_logic_arith
o-work DATAPATH_LIB -O0
tExplicit 1 GenerateLoopIterationMax 100000
Eselector
w1127037318
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
FH:/MODELSIM/VHDL-Lab4/selector.vhd
l0
L6
V2Y5He_UO3hWFID4Gc6_9f3
OV;C;6.0c;29
32
o-work DATAPATH_LIB -O0
tExplicit 1 GenerateLoopIterationMax 100000
Abehaviour
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work selector 2Y5He_UO3hWFID4Gc6_9f3
l21
L19
V@T]5Gj54eVZM_QdPbfK4X2
OV;C;6.0c;29
32
M1 ieee std_logic_1164
o-work DATAPATH_LIB -O0
tExplicit 1 GenerateLoopIterationMax 100000
Eshifter
w1127037318
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
FH:/MODELSIM/VHDL-Lab4/shifter.vhd
l0
L6
V<Nj]KQm;dRA;bCM;DfM1Z1
OV;C;6.0c;29
32
o-work DATAPATH_LIB -O0
tExplicit 1 GenerateLoopIterationMax 100000
Abehaviour
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work shifter <Nj]KQm;dRA;bCM;DfM1Z1
l20
L18
V_n@:L2E?L_RekQk]kU2YT1
OV;C;6.0c;29
32
M1 ieee std_logic_1164
o-work DATAPATH_LIB -O0
tExplicit 1 GenerateLoopIterationMax 100000