regfile.vhd

&#65279 The purpose of this lab is to introduce the concept of FSMs with a datapath, and to stud

USE WORK.ALL;

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_signed.all;
USE IEEE.std_logic_arith.all;

ENTITY regFile IS
  GENERIC (
    Size  : INTEGER; -- # bits in word
    ASize : INTEGER  -- # bits in address
  );
  PORT (
    RegIn   : IN  STD_LOGIC_VECTOR(Size-1 DOWNTO 0);

    RegAOut : OUT STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
    RegBOut : OUT STD_LOGIC_VECTOR(Size-1 DOWNTO 0);

    Clk     : IN  STD_LOGIC;

    WAddr   : IN  STD_LOGIC_VECTOR(ASize-1 DOWNTO 0);
    WEnabl  : IN  STD_LOGIC;

    RAddrA  : IN  STD_LOGIC_VECTOR(ASize-1 DOWNTO 0);
    REnablA : IN  STD_LOGIC;

    RAddrB  : IN  STD_LOGIC_VECTOR(ASize-1 DOWNTO 0);
    REnablB : IN  STD_LOGIC
  );
END regFile;

ARCHITECTURE behaviour OF regFile IS

SUBTYPE Reg_Type     IS STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
TYPE    RegFile_Type IS ARRAY(2**ASize-1 DOWNTO 0) OF Reg_Type;

SIGNAL RegFile : RegFile_Type;

BEGIN


  PROCESS(Clk)

  BEGIN

    IF Clk'EVENT AND Clk = '1' THEN
      IF WEnabl = '1' THEN 
        RegFile(CONV_INTEGER(UNSIGNED(WAddr))) <= RegIn;
      ELSE
        Null;
      END IF;
    END IF;

  END PROCESS;

  PROCESS(REnablA,REnablB,RAddrA,RAddrB,RegFile)

  BEGIN

      IF REnablA = '1' THEN
        RegAOut  <= RegFile(CONV_INTEGER(UNSIGNED(RAddrA)));
      ELSE
        RegAOut  <= (OTHERS => 'Z');
      END IF;

      IF REnablB = '1' THEN 
        RegBOut  <= RegFile(CONV_INTEGER(UNSIGNED(RAddrB)));
      ELSE
        RegBOut  <= (OTHERS => 'Z');
      END IF;

  END PROCESS;
END behaviour;