shifter.vhd

&#65279 The purpose of this lab is to introduce the concept of FSMs with a datapath, and to stud

USE WORK.ALL;

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY shifter IS
  GENERIC (
    Size: INTEGER
  );
  PORT (
    A     : IN  STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
    Ctrl  : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);

    Q     : OUT STD_LOGIC_VECTOR(Size-1 DOWNTO 0)
  );
END shifter;

ARCHITECTURE behaviour OF shifter IS

BEGIN

  PROCESS(A,Ctrl)

  BEGIN

    CASE Ctrl is
      WHEN "000" =>  Q                  <= A;
      WHEN "001" =>  Q                  <= A;
      WHEN "010" =>  Q                  <= A;
      WHEN "011" =>  Q                  <= A;
      WHEN "100" =>  Q                  <= A(Size-2 DOWNTO 0) & '0';
      WHEN "101" =>  Q(Size-1 DOWNTO 1) <= A(Size-2 DOWNTO 0);
		     Q(0)               <= A(Size-1);
      WHEN "110" =>  Q                  <= '0' & A(Size-1 DOWNTO 1);
      WHEN "111" =>  Q(Size-2 DOWNTO 0) <= A(Size-1 DOWNTO 1);
		     Q(Size-1)          <= A(0);

      WHEN OTHERS => ASSERT false report "Ctrl out of range, testbench error"severity error;
    END CASE;

  END PROCESS;
END behaviour;