datapath.vhd

&#65279 The purpose of this lab is to introduce the concept of FSMs with a datapath, and to stud

USE WORK.ALL;
USE WORK.package_MicroAssemblyCode.ALL;

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY dataPath IS
  GENERIC (
    Size  : INTEGER := 8; -- # bits in word
    ASize : INTEGER := 3  -- # bits in address
  );
  PORT (
    InPort      : IN  STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
    OutPort     : OUT STD_LOGIC_VECTOR(Size-1 DOWNTO 0);

    Clk         : IN  STD_LOGIC;

    Instr       : IN Instruction_type);-- :=( '0' , Rx   , Rx   , Rx   , OpX   , OpX     , '0' ));
END dataPath;

ARCHITECTURE behaviour OF dataPath IS

COMPONENT selector
  GENERIC (
    Size: INTEGER
  );
  PORT (
    A     : IN  STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
    B     : IN  STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
    Ctrl  : IN  STD_LOGIC;

    Q     : OUT STD_LOGIC_VECTOR(Size-1 DOWNTO 0)
  );
END COMPONENT;

COMPONENT regFile 
  GENERIC (
    Size  : INTEGER; -- # bits in word
    ASize : INTEGER  -- # bits in address
  );
  PORT (
    RegIn   : IN  STD_LOGIC_VECTOR(Size-1 DOWNTO 0);

    RegAOut : OUT STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
    RegBOut : OUT STD_LOGIC_VECTOR(Size-1 DOWNTO 0);

    Clk     : IN  STD_LOGIC;

    WAddr   : IN  STD_LOGIC_VECTOR(ASize-1 DOWNTO 0);
    WEnabl  : IN  STD_LOGIC;

    RAddrA  : IN  STD_LOGIC_VECTOR(ASize-1 DOWNTO 0);
    REnablA : IN  STD_LOGIC;

    RAddrB  : IN  STD_LOGIC_VECTOR(ASize-1 DOWNTO 0);
    REnablB : IN  STD_LOGIC
  );
END COMPONENT;

COMPONENT alu
  GENERIC (
    Size: INTEGER
  );
  PORT (
    A     : IN  STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
    B     : IN  STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
    Ctrl  : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);

    Carry : OUT STD_LOGIC;		
    Q     : OUT STD_LOGIC_VECTOR(Size-1 DOWNTO 0)
  );
END COMPONENT; 

COMPONENT shifter
  GENERIC (
    Size: INTEGER
  );
  PORT (
    A     : IN  STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
    Ctrl  : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);

    Q     : OUT STD_LOGIC_VECTOR(Size-1 DOWNTO 0)
  );
END COMPONENT;

SIGNAL     select_out : STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
SIGNAL     result_bus : STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
SIGNAL     bus_a      : STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
SIGNAL     bus_b      : STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
SIGNAL     alu_out    : STD_LOGIC_VECTOR(Size-1 DOWNTO 0);

ALIAS      IE         : STD_LOGIC IS Instr.IE;
ALIAS      WAddr      : STD_LOGIC_VECTOR(ASize-1 DOWNTO 0) IS Instr.Dest(ASize DOWNTO 1);
ALIAS      WEnabl     : STD_LOGIC IS Instr.Dest(0);

ALIAS      RAddrA     : STD_LOGIC_VECTOR(ASize-1 DOWNTO 0) IS Instr.Src1(ASize DOWNTO 1);
ALIAS      REnablA    : STD_LOGIC IS Instr.Src1(0);

ALIAS      RAddrB     : STD_LOGIC_VECTOR(ASize-1 DOWNTO 0) IS Instr.Src2(ASize DOWNTO 1);
ALIAS      REnablB    : STD_LOGIC IS Instr.Src2(0);

ALIAS      AluCtrl    : STD_LOGIC_VECTOR(2 DOWNTO 0) IS Instr.Alu;
ALIAS      ShifterCtrl: STD_LOGIC_VECTOR(2 DOWNTO 0) IS Instr.Shift;

ALIAS      OE	    : STD_LOGIC IS Instr.OE;

BEGIN

  PROCESS(result_bus,OE)

  BEGIN

    IF OE = '1' THEN 
      OutPort <= result_bus;
    ELSE
      OutPort <= (OTHERS => 'Z');
    END IF;

  END PROCESS;


  U_selector : selector
    GENERIC MAP(Size => Size
    )
    PORT    MAP(A    => InPort,
                B    => result_bus,
                Ctrl => IE,
                Q    => select_out
    );

  U_regFile : regFile
    GENERIC MAP(Size  => Size,
                ASize => ASize
    )
    PORT    MAP(RegIn   => select_out,
                RegAOut => bus_a,
                RegBOut => bus_b,
                Clk     => Clk, 
                WAddr   => WAddr,
                WEnabl  => WEnabl,
                RAddrA  => RAddrA,
                REnablA => REnablA,
                RAddrB  => RAddrB,
                REnablB => REnablB
     );

  U_alu : alu
    GENERIC MAP(Size  => Size
    )
    PORT    MAP(A     => bus_a,
                B     => bus_b,
                Ctrl  => ALuCtrl,
                Carry => Open,
                Q     => alu_out
    );

  U_shifter : shifter
    GENERIC MAP(Size  => Size
    )
    PORT    MAP(A     => alu_out,
                Ctrl  => ShifterCtrl,
                Q     => result_bus 
  );

END behaviour;