alu.vhd

&#65279 The purpose of this lab is to introduce the concept of FSMs with a datapath, and to stud

USE WORK.ALL;

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;

ENTITY alu IS
  GENERIC (
    Size: INTEGER
  );
  PORT (
    A     : IN  STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
    B     : IN  STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
    Ctrl  : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);

    Carry : OUT STD_LOGIC;		
    Q     : OUT STD_LOGIC_VECTOR(Size-1 DOWNTO 0)
  );
END alu;

ARCHITECTURE behaviour OF alu IS

BEGIN

  PROCESS(A,B,Ctrl)

    VARIABLE a_int : STD_LOGIC_VECTOR(Size DOWNTO 0); -- := '0' & A; ???
    VARIABLE b_int : STD_LOGIC_VECTOR(Size DOWNTO 0); -- := '0' & B; ???

  BEGIN

    a_int := '0' & A;
    b_int := '0' & B;

    Carry <= '0';

    CASE Ctrl is
      WHEN "000" =>  Q     <= NOT A;
      WHEN "001" =>  Q     <= A AND B;
      WHEN "010" =>  Q     <= A XOR B;
      WHEN "011" =>  Q     <= A OR B;
      WHEN "100" =>  Q     <= CONV_STD_LOGIC_VECTOR(SIGNED(a_Int)-1,Size+1)(Size-1 DOWNTO 0);
      WHEN "101" =>  Q     <= CONV_STD_LOGIC_VECTOR(SIGNED(a_Int)+SIGNED(b_Int),Size+1)(Size-1 DOWNTO 0);
                     Carry <= CONV_STD_LOGIC_VECTOR(SIGNED(a_Int)+SIGNED(b_Int),Size+1)(Size);
      WHEN "110" =>  Q     <= CONV_STD_LOGIC_VECTOR(SIGNED(a_Int)-SIGNED(b_Int),Size+1)(Size-1 DOWNTO 0);
                     Carry <= CONV_STD_LOGIC_VECTOR(SIGNED(a_Int)-SIGNED(b_Int),Size+1)(Size);
      WHEN "111" =>  Q     <= CONV_STD_LOGIC_VECTOR(SIGNED(a_Int)+1,Size+1)(Size-1 DOWNTO 0);

      WHEN OTHERS => ASSERT false report "Ctrl out of range, testbench error"severity error;
    END CASE;

  END PROCESS;
END behaviour;