videocomposer_fpga.vhd

&#65279 The purpose of this lab is to introduce the concept of FSMs with a datapath, and to stud

------------------VideoComposer_fpga-------------------
------------------VideoComposer_fpga-------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;  -- contains some conversion functions
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
--USE Std.TextIO.ALL;
USE WORK.ALL;
USE WORK.package_MicroAssemblyCode.ALL;


--library DATAPATH_LIB;                   -- contains Datapath entities and 
--use DATAPATH_LIB.all;                   -- architectures
--use DATAPATH_LIB.package_MicroAssemblyCode.all;

USE WORK.ALL;
ENTITY videoComposer_fpga IS
   GENERIC (
   Size : INTEGER:=8; -- # bits in word
   ASize : INTEGER:=3 -- # bits in address
   );
   PORT (
   Clk : IN STD_LOGIC;
   Reset : IN STD_LOGIC;
   Ready : OUT STD_LOGIC;
   q : OUT STD_LOGIC_VECTOR(7 downto 0)
   );
END videoComposer_fpga;

ARCHITECTURE behaviour OF videoComposer_fpga IS
CONSTANT ROM : Program_Type := (
--| IE | Dest | Src1 | Src2 | OpAlu | OpShift | OE |
('1',R1,Rx,Rx,OpAnd,OpPass,'0'),--0 ReadRed => -- ROM Instr 0
('0',R0,R1,R1,OpXor,OpPass,'0'),--1 Reset R0=0
('1',R2,R1,R0,OpAdd,OpPass,'1'),--2 ReadGreenWriteRed => -- ROM Instr 1
('1',R3,R2,R0,OpAdd,OpPass,'1'),--3 ReadBlueWriteGreen => -- ROM Instr 2

('0',R3,R3,R0,OpAdd,OpRotL,'0'),--4 ProcessBlue => -- ROM Instr 4-8 
                                 --1st rotate left
('0',R3,R3,R0,OpAdd,OpRotL,'0'),--5 2nd rotate left 
('0',R4,R0,Rx,OpInc,OpRotL,'0'),--6 mask1=00000010              
('0',R4,R4,Rx,OpInc,OpPass,'0'),--7 mask1=00000011

('0',R6,R3,R4,OpAnd,OpPass,'0'),--8 tmp=B' and mask1
('0',Rx,R6,R0,OpAdd,OpPass,'1'),--9 tmp-->outport judge 
('0',Rx,R3,R0,OpAdd,OpPass,'1'),--10 outport='00000000',so out R3
    
('0',Rx,R0,Rx,Opdec,OpPass,'1'),--11 outport/='00000000',so out '11111111'
                                --saturate
('0',Rx,Rx,Rx,OpAnd,OpPass,'0'), --12-NULL OPERATION
('0',Rx,Rx,Rx,OpAnd,OpPass,'0'), --13-NULL OPERATION
('0',Rx,Rx,Rx,OpAnd,OpPass,'0'), --14-NULL OPERATION
('0',Rx,Rx,Rx,OpAnd,OpPass,'0')  --15-NULL OPERATION

);

COMPONENT dataPath
GENERIC (
Size : INTEGER := 8; -- # bits in word
ASize : INTEGER := 3 -- # bits in address
);
PORT (
InPort : IN STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
OutPort : OUT STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
Clk : IN STD_LOGIC;
Instr : IN Instruction_Type
);
END COMPONENT;

--COMPONENT single_port_ram
--PORT
--(
--...
--);
--END COMPONENT;
COMPONENT single_port_rom
PORT
(
		address		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);--4096 addresses
		--inclock		: IN STD_LOGIC ;
		--outclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);

END COMPONENT;
-- Datapath signals
SIGNAL in_port : STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
SIGNAL out_port : STD_LOGIC_VECTOR(Size-1 DOWNTO 0);
SIGNAL instr : Instruction_type := ( '0' , Rx , Rx , Rx , OpX , OpX , '0' );
TYPE State_Type IS (reset_state,S_ReadRed,S_ResetR0, S_ReadGreenWriteRed, S_ReadBlueWriteGreen,
S_ProcessBlue, S_WriteBlue, S_Idle);
SIGNAL current_state, next_state : State_Type;
-- Instr counter for the datapath
SIGNAL current_counter, next_counter : INTEGER := 0;
SIGNAL read_address,next_read_address,write_address,next_write_address:
STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL read_data,write_data_out:STD_LOGIC_VECTOR(7 downto 0);
SIGNAL wr_en,wr_ram:STD_LOGIC:='0';

BEGIN
   instr <= ROM(current_counter);
   in_port <= read_data;
   COMB: PROCESS(current_state, current_counter, read_address, write_address,
   read_data,out_port)
BEGIN
   next_state <= current_state;
   next_counter <= current_counter;
   Ready <= '0';
   next_read_address<=(others=>'0');
   next_write_address<=(others=>'0');
   wr_en<='0';
   CASE current_state IS
      WHEN reset_state =>
         next_read_address<=(others=>'0');
         next_write_address<=(others=>'0');
         wr_en<='0';
         next_state<=S_ReadRed;
         next_counter <= 0;
  
      WHEN S_ReadRed => -- ROM Instr 0
         next_state<=S_ResetR0;--S_ReadGreenWriteRed;
         next_counter <= 1;
         next_read_address<=read_address+1;--put this in S_resetR0 is also rt!!
       when s_ResetR0=> --  set R0=0;
        next_state<=S_ReadGreenWriteRed;
        next_counter <= 2;
        wr_en<='1';---here!!!
      WHEN S_ReadGreenWriteRed => -- ROM Instr 2
         --wr_en<='1'; ---move up to prevous state.
         wr_en<='1';
         next_counter <= 3;
         next_state <= S_ReadBlueWriteGreen;
         next_read_address<=read_address+1;
         next_write_address<=write_address+1;
      WHEN S_ReadBlueWriteGreen => -- ROM Instr 3
         --wr_en<='1'; ---move up to prevous state.
         next_counter <= 4;
         next_state <= S_ProcessBlue;
         next_read_address<=read_address+1;
         next_write_address<=write_address+1;
      WHEN S_ProcessBlue => -- ROM Instr 4-8
         IF current_counter < 9 THEN
            next_counter <= current_counter + 1;
            next_state <= S_ProcessBlue;
         ELSE
            IF out_port = "00000000" THEN
               next_counter <= 10;
            ELSE
               next_counter <= 11;
            END IF;
            next_state <= S_WriteBlue;
         END IF;
      WHEN S_WriteBlue => -- ROM Instr 10 or 11
         wr_en<='1';
         next_write_address<=write_address+1;
         next_state <= S_Idle;------
         -----------------------
         ---------------should next_counter leave don't care???         
         ----if not alway run output blue to outport...
         ----because  next_counter <= 11; in last state.
         next_counter<=15;----so add one...
         
      WHEN S_Idle =>
         if (read_address=57600) then----impossible to reach???
                                       --rom_size is 4096Byte=4k
                                       --max address is 4095...
            Ready <= '1';
         else
            next_state<=S_ReadRed;
            next_counter<=0;
         end if;
      WHEN OTHERS =>
         ASSERT false
         report "illegal FSM state, testbench error"
         severity error;
      END CASE;
END PROCESS;

P_SYNCH: PROCESS(Clk,reset)
BEGIN
IF (reset='0') then
   current_state<=reset_state;
   current_counter<=0;
ELSIF Clk'EVENT AND Clk = '1' THEN
   read_address <= next_read_address;
   write_address <= next_write_address;
   current_state <= next_state;
   current_counter <= next_counter;
END IF;
END PROCESS;

U_dataPath : dataPath
GENERIC MAP(Size => Size, ASize => ASize)
PORT MAP( InPort => in_port,
         OutPort => out_port,
         Clk     => Clk,
         Instr   => instr);

Read_ROM:single_port_rom port map (read_address,read_data);

--Write_RAM:single_port_ram port map (write_address,wr_ram,out_port,q);

-- Ensure a late cycle write to allow address to change first
--wr_ram<=wr_en AND not(clk);
q<=out_port;
END behaviour;