_info

&#65279 The purpose of this lab is to introduce the concept of FSMs with a datapath, and to stud

m255
13
cModel Technology
dD:\vhdl\lab4_new
Ealu
w1127037318
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\vhdl\xx_new4
FD:/vhdl/xx/alu.vhd
l0
L7
V4i;HEQ3XSY@>GK[m?i[]F3
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Abehaviour
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work alu 4i;HEQ3XSY@>GK[m?i[]F3
l23
L21
VL3g>^EdLiTQChK=YUcz7P3
OE;C;6.0;29
32
M2 ieee std_logic_1164
M1 ieee std_logic_arith
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Edatapath
w1127037318
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DP work package_microassemblycode clWHE8X0I:Wk68Q8FGJbM3
dD:\vhdl\xx_new4
FD:/vhdl/xx/dataPath.vhd
l0
L7
V?TO]6jT]a9d>D]cNcGi7B1
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Abehaviour
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DP work package_microassemblycode clWHE8X0I:Wk68Q8FGJbM3
DE work datapath ?TO]6jT]a9d>D]cNcGi7B1
l107
L21
VQm5oig3D4FhnijZj[N[=F2
OE;C;6.0;29
32
M2 work package_microassemblycode
M1 ieee std_logic_1164
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Ppackage_microassemblycode
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
w1127037318
dD:\vhdl\xx_new4
FD:/vhdl/xx/package_microAssemblyCode.vhd
l0
L6
VclWHE8X0I:Wk68Q8FGJbM3
OE;C;6.0;29
32
M1 ieee std_logic_1164
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Eregfile
w1127037318
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_signed <9<Kcl:S52:oW`F]FQhb20
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\vhdl\xx_new4
FD:/vhdl/xx/regFile.vhd
l0
L8
VVg?b5I[S69QQ[B0o9OAQa1
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Abehaviour
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_signed <9<Kcl:S52:oW`F]FQhb20
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work regfile Vg?b5I[S69QQ[B0o9OAQa1
l39
L32
VaBTTQf?Bojcz1lhaGl>ZQ0
OE;C;6.0;29
32
M3 ieee std_logic_1164
M2 ieee std_logic_signed
M1 ieee std_logic_arith
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Eselector
w1127037318
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\vhdl\xx_new4
FD:/vhdl/xx/selector.vhd
l0
L6
V2Y5He_UO3hWFID4Gc6_9f3
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Abehaviour
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work selector 2Y5He_UO3hWFID4Gc6_9f3
l21
L19
V@T]5Gj54eVZM_QdPbfK4X2
OE;C;6.0;29
32
M1 ieee std_logic_1164
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Eshifter
w1127037318
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\vhdl\xx_new4
FD:/vhdl/xx/shifter.vhd
l0
L6
V<Nj]KQm;dRA;bCM;DfM1Z1
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Abehaviour
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work shifter <Nj]KQm;dRA;bCM;DfM1Z1
l20
L18
V_n@:L2E?L_RekQk]kU2YT1
OE;C;6.0;29
32
M1 ieee std_logic_1164
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Esingle_port_rom
w1160048098
DP lpm lpm_components iWB`dLH:QY^2b_X4X@z9_1
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\vhdl\xx_new4
FD:/vhdl/xx/single_port_rom.vhd
l0
L39
VSRmE;1gKULnJ=JNmCJ6`;2
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Asyn
DP lpm lpm_components iWB`dLH:QY^2b_X4X@z9_1
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work single_port_rom SRmE;1gKULnJ=JNmCJ6`;2
l71
L48
V@V`SWNmFLA_<ekhAO<Xg<3
OE;C;6.0;29
32
M2 ieee std_logic_1164
M1 lpm lpm_components
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Etb_videocomposer_93
w1067245894
DP datapath_lib package_microassemblycode clWHE8X0I:Wk68Q8FGJbM3
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\vhdl\xx_new4
FD:/vhdl/xx/tb_videoComposer_93.vhd
l0
L12
VNC[XgF[D_PUkMD@bjoL783
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Atb_behaviour
DP ieee std_logic_signed <9<Kcl:S52:oW`F]FQhb20
DP datapath_lib package_microassemblycode clWHE8X0I:Wk68Q8FGJbM3
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work tb_videocomposer_93 NC[XgF[D_PUkMD@bjoL783
l190
L15
VoR2eN6X0UZGmMj^HX<6gI2
OE;C;6.0;29
32
M5 ieee std_logic_1164
M4 ieee std_logic_arith
M3 std textio
M2 datapath_lib package_microassemblycode
M1 ieee std_logic_signed
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Evideocomposer
w1159992408
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DP work package_microassemblycode clWHE8X0I:Wk68Q8FGJbM3
dD:\vhdl\xx_new4
FD:/vhdl/xx/videocomposer.vhd
l0
L6
VlbJh[3;oik[zUeFlAP0^a0
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Acomposite
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DP work package_microassemblycode clWHE8X0I:Wk68Q8FGJbM3
DE work videocomposer lbJh[3;oik[zUeFlAP0^a0
l75
L21
V@:KS<^X^OAI1Q3Ua^TCi41
OE;C;6.0;29
32
M3 work package_microassemblycode
M2 ieee std_logic_1164
M1 ieee std_logic_arith
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Evideocomposer_fpga
w1159992232
DP work package_microassemblycode clWHE8X0I:Wk68Q8FGJbM3
DP ieee std_logic_signed <9<Kcl:S52:oW`F]FQhb20
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\vhdl\xx_new4
FD:/vhdl/xx/videoComposer_fpga.vhd
l0
L17
V1d0MF7?SSaG:ZfNWWlkc11
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Abehaviour
DP work package_microassemblycode clWHE8X0I:Wk68Q8FGJbM3
DP ieee std_logic_signed <9<Kcl:S52:oW`F]FQhb20
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work videocomposer_fpga 1d0MF7?SSaG:ZfNWWlkc11
l100
L30
V[Ge0c8mhaOQhQ`HmFf55I0
OE;C;6.0;29
32
M4 ieee std_logic_1164
M3 ieee std_logic_arith
M2 ieee std_logic_signed
M1 work package_microassemblycode
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000