📄 str75x.s
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Vectors LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr
LDR PC, DAbt_Addr
NOP ; Reserved Vector
IF EIC_SETUP != 0
LDR PC, IRQ_Addr
ELSE
LDR PC,[PC, #-0x0808] ; Vector from EIC_IVR
ENDIF
LDR PC, FIQ_Addr
Reset_Addr DCD Reset_Handler
Undef_Addr DCD UndefHandler
SWI_Addr DCD SWIHandler
PAbt_Addr DCD PAbtHandler
DAbt_Addr DCD DAbtHandler
DCD 0 ; Reserved Address
IRQ_Addr DCD IRQHandler
FIQ_Addr DCD FIQHandler
IF EIC_SETUP = 0
UndefHandler B UndefHandler
SWIHandler B SWIHandler
PAbtHandler B PAbtHandler
DAbtHandler B DAbtHandler
IRQHandler B IRQHandler
FIQHandler B FIQHandler
ELSE
; Peripherals IRQ Handlers Address Table
WAKUP_Addr DCD WAKUP_IRQHandler
TIM2_OC2_Addr DCD TIM2_OC2_IRQHandler
TIM2_OC1_Addr DCD TIM2_OC1_IRQHandler
TIM2_IC12_Addr DCD TIM2_IC12_IRQHandler
TIM2_UP_Addr DCD TIM2_UP_IRQHandler
TIM1_OC2_Addr DCD TIM1_OC2_IRQHandler
TIM1_OC1_Addr DCD TIM1_OC1_IRQHandler
TIM1_IC12_Addr DCD TIM1_IC12_IRQHandler
TIM1_UP_Addr DCD TIM1_UP_IRQHandler
TIM0_OC2_Addr DCD TIM0_OC2_IRQHandler
TIM0_OC1_Addr DCD TIM0_OC1_IRQHandler
TIM0_IC12_Addr DCD TIM0_IC12_IRQHandler
TIM0_UP_Addr DCD TIM0_UP_IRQHandler
PWM_OC123_Addr DCD PWM_OC123_IRQHandler
PWM_EM_Addr DCD PWM_EM_IRQHandler
PWM_UP_Addr DCD PWM_UP_IRQHandler
I2C_Addr DCD I2C_IRQHandler
SSP1_Addr DCD SSP1_IRQHandler
SSP0_Addr DCD SSP0_IRQHandler
UART2_Addr DCD UART2_IRQHandler
UART1_Addr DCD UART1_IRQHandler
UART0_Addr DCD UART0_IRQHandler
CAN_Addr DCD CAN_IRQHandler
USB_LP_Addr DCD USB_LP_IRQHandler
USB_HP_Addr DCD USB_HP_IRQHandler
ADC_Addr DCD ADC_IRQHandler
DMA_Addr DCD DMA_IRQHandler
EXTIT_Addr DCD EXTIT_IRQHandler
MRCC_Addr DCD MRCC_IRQHandler
FLASHSMI_Addr DCD FLASHSMI_IRQHandler
RTC_Addr DCD RTC_IRQHandler
TB_Addr DCD TB_IRQHandler
ENDIF
; Code Start - Reset Handler ---------------------------------------------------
EXPORT Reset_Handler
Reset_Handler
; Wait for clock to stabilize --------------------------------------------------
LDR R1, =10000
WAIT SUBS R1, R1, #1
BNE WAIT
; Setup Global Configuration Register ------------------------------------------
IF GLBCONF_SETUP != 0
LDR R0, =CFG_GLCONF_ADR
LDR R1, [R0]
LDR R2, =CFG_GLCONF_Val
BIC R1, R1, #0x0300
ORR R1, R1, R2
STR R1, [R0]
ENDIF
; MCU Reset and Clock Control --------------------------------------------------
IF CLOCK_SETUP != 0
IF MRCC_SETUP != 0
; Setup peripheral clock dividers
LDR R0, =MRCC_BASE
LDR R1, =MRCC_CLKCTL_Val
LDR R2, [R0, #MRCC_CLKCTL_OFS] ; load current CLKCTL value
LDR R5, =DIV_MASK
MVN R6, R5
AND R5, R1, R5
AND R6, R2, R6
ORR R5, R5, R6
STR R5, [R0, #MRCC_CLKCTL_OFS] ; load div values
; if OSC4M is used as system clock source (OSC_4M as CK_SYS) ---
IF (MRCC_CLKCTL_Val:AND:CKOSCSEL_BIT) = 0
LDR R2, [R0, #MRCC_CLKCTL_OFS] ; Wait presence of osc clk
BIC R2, R2, #NCKDF_BIT
WAIT_OSC_PRES STR R2, [R0, #MRCC_CLKCTL_OFS] ; Write 0 to NCKDF Flag
LDR R1, [R0, #MRCC_CLKCTL_OFS] ; Read NCKDF Flag
ANDS R1, R1, #NCKDF_BIT
BNE WAIT_OSC_PRES ; if NCKDF Flag set to 1
WAIT_CLK_STABIL LDR R1, [R0, #MRCC_RFSR_OFS] ; Wait stabil clock
ANDS R1, R1, #BCOUNTF_BIT
BEQ WAIT_CLK_STABIL
LDR R1, [R0, #MRCC_CLKCTL_OFS] ; Switch CK_SYS to CK_OSC4M
ORR R2, R1, #CKSEL_BIT
STR R2, [R0, #MRCC_CLKCTL_OFS]
; if PLL is used as system clock source (PLL as CK_SYS) ----
IF (MRCC_CLKCTL_Val:AND:CKSEL_BIT) = 0
; PLL is by default disabled
; Setup PLL multiply factor
LDR R1, =MRCC_CLKCTL_Val
LDR R2, [R0, #MRCC_CLKCTL_OFS] ; load current CLKCTL value
LDR R3, =MUL_MASK
MVN R4, R3
AND R3, R1, R3
AND R4, R2, R4
ORR R3, R3, R4
STR R3, [R0, #MRCC_CLKCTL_OFS] ; load mul value
LDR R1, [R0, #MRCC_CLKCTL_OFS] ; Enable the PLL
ORR R1, R1, #PLL_EN_BIT
STR R1, [R0, #MRCC_CLKCTL_OFS]
PLL_LOCKING LDR R1, [R0, #MRCC_CLKCTL_OFS] ; Wait for PLL to lock
ANDS R1, R1, #PLL_LOCK_BIT
BEQ PLL_LOCKING
; if PLL2EN is used set it after PLL is locked ----
IF (MRCC_CLKCTL_Val:AND:PLL2_EN_BIT) != 0
LDR R1, [R0, #MRCC_CLKCTL_OFS] ; Enable the PLL2EN
ORR R1, R1, #PLL2_EN_BIT
STR R1, [R0, #MRCC_CLKCTL_OFS]
ENDIF ; ------------------------------------------
LDR R1, [R0, #MRCC_CLKCTL_OFS] ; Switch CK_SYS to CK_PLL1
BIC R1, R1, #CKSEL_BIT
STR R1, [R0, #MRCC_CLKCTL_OFS]
ENDIF ; --------------------------------------------------
ENDIF ; ------------------------------------------------------
ENDIF
; Enable peripheral clocks if requested
IF MRCC_PCLKEN_Val != 0
LDR R0, =MRCC_BASE
LDR R1, =MRCC_PCLKEN_Val
STR R1, [R0, #MRCC_PCLKEN_OFS] ; Enable Peripheral Clocks
ENDIF
IF PERIPH_RESET != 0 ; Reset Peripherals
LDR R0, =MRCC_BASE
LDR R1, =PERIPH_MASK
MOV R2, #0
STR R1, [R0, #MRCC_PSWRES_OFS] ; Put Periphs Under Reset
NOP ; Wait for Periphs to Reset
NOP
NOP
NOP
STR R2, [R0, #MRCC_PSWRES_OFS] ; Release Periphs Reset
ENDIF
IF BKP_SETUP != 0 ; Setup Backup Registers
LDR R0, =MRCC_BASE
LDR R1, =MRCC_BKP0_Val
STR R1, [R0, #MRCC_BKP0_OFS] ; Backup Register 0
LDR R1, =MRCC_BKP1_Val
STR R1, [R0, #MRCC_BKP1_OFS] ; Backup Register 1
ENDIF
ENDIF ; for CLOCK_SETUP
; Setup Serial Memory Interface (SMI) ------------------------------------------
IF SMI_SETUP != 0
LDR R0, =GPIO_BASE ; Setup GPIO port functions for SM
MOV R1, #GPIO_REMAP0R_Val
LDR R1, [R0, #GPIO_REMAP0R_OFS]
LDR R0, =SMI_BASE ; Setup SMI
LDR R1, =SMI_CR1_Val
LDR R2, =SMI_CR2_Val
STR R1, [R0, #SMI_CR1_OFS]
STR R2, [R0, #SMI_CR2_OFS]
ENDIF
; Setup Enhanced Interrupt Controller (EIC) ------------------------------------
IF EIC_SETUP != 0
LDR R0, =EIC_BASE
LDR R1, =0xE59F0000 ; LDR PC,[PC,#ofs] (High 16-bits)
STR R1, [R0, #EIC_IVR_OFS] ; Store into IVR[31:16]
LDR R1, =WAKUP_Addr ; IRQ Address Table
LDR R2, =0x0FFF ; Offset Mask
AND R1, R1, R2 ; Mask Offset
LDR R2, =0xF7E0 ; Jump Offset = 0x07E0
; 0xFXXX is used to complete the
; LDR PC,[PC,#ofs]
; 0x07E0 = 0x07E8 - 8 (Prefetch)
; 0 = IVR Address + 0x7E8
ADD R1, R1, R2 ; Add Jump Offset
MOV R2, #32 ; Number of Channels
MOV R3, #EIC_SIR0_OFS ; Offset to SIR0
EIC_Loop MOV R4, R1, LSL #16 ; Use High 16-bits
STR R4, [R0, R3] ; Store into SIRx
ADD R1, R1, #4 ; Next IRQ Address
ADD R3, R3, #4 ; Next SIRx
SUBS R2, R2, #1 ; Decrement Counter
BNE EIC_Loop
ENDIF
; Memory Remap -----------------------------------------------------------------
FLASH_BM EQU 0x00 ; Boot Mode: Int Flash at 0
SYSMEM_BM EQU 0x01 ; Boot Mode: System Memory at 0
RAM_BM EQU 0x02 ; Boot Mode: Int SRAM at 0
EXT_SEEPROM_BM EQU 0x03 ; Boot Mode: Ext Serial EEPROM at 0
EXT_SFLASH_BM EQU 0x07 ; Boot Mode: Ext Serial Flash at 0
IF :DEF:REMAP
MOV R1, #FLASH_BM
IF :DEF:SYSMEM_MODE
MOV R1, #SYSMEM_BM
ELIF :DEF:RAM_MODE
MOV R1, #RAM_BM
ELIF :DEF:EXT_SEEPROM_MODE
MOV R1, #EXT_SEEPROM_BM
ELIF :DEF:EXT_SFLASH_MODE
MOV R1, #EXT_SFLASH_BM
ENDIF
LDR R0, =CFG_GLCONF_ADR
LDR R2, [R0] ; Read CFG_GLCONF
BIC R2, R2, #0x07 ; Clear three LSB bits
ORR R2, R2, R1 ; Setup three LSB bits
STR R2, [R0] ; Write CFG_GLCONF
ENDIF
; Reset Handler ----------------------------------------------------------------
LDR R0, =Stack_Top
; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
; Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
; Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
; Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
; Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
; Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
MOV SP, R0
SUB SL, SP, #USR_Stack_Size
; Enter the C code
IMPORT __main
LDR R0, =__main
BX R0
; User Initial Stack & Heap
AREA |.text|, CODE, READONLY
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + USR_Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
END
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