📄 flashat91sam7.mac
字号:
// ---------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: FlashAT91SAM7.mac
//
// User setup file for CSPY debugger to simulate interrupt
// driven Fibonacchi data input.
// 1.1 18/Aug/04 JPP : Creation
// 1.2 27/Aug/04 JPP : PLL setting
// 1.3 04/Apr/05 JPP : Change variable name
// 1.4 08/Sep/05 JPP : Set AT91F_LowLevelInit
// 1.5 14/Nov/05 JPP : RTC setting : suppress all PLL init
// this file must be remplace the same file located in the
// IAR inatallation IAR-KS-4_30A\arm\config\flashloader\Atmel
//
// this fife can be used for:
// AT91SAM7S family, 32,321,64,126,256
// FlashAT91SAM7Sx.mac
// FlashAT91SAM7Sxx.mac
// AT91SAM7A3
// FlashAT91SAMA3.mac
// AT91SAM7X 128,256 and AT91SAM7XC 128,256
// FlashAT91SAM7X.mac
//
// $Revision: 1.2 $
//
// ---------------------------------------------------------
__var __mac_i;
__var __mac_pt;
__var __mac_mem;
__var __mac_Trace;
execUserFlashInit()
{
__hwReset(0);
__emulatorSpeed(30000); // Set JTAG speed to 30kHz to make a hardware reset
__message " ---------------------------------------- FLASH Download V1.3";
__message " ---------------------------------------- 14/Nov/2005";
_PllSetting();
execUserPreload();
execUserSetup();
}
execUserPreload()
{
//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
_CheckNoRemap();
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
_Chip_ID();
if (__mac_mem !=0)
{
__message " ---------------------------------------- AT91SAM7X device";
_InitFlash();
}
//* Get the chip status
//* Watchdog Disable AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS
__writeMemory32(0x00008000,0xFFFFFD44,"Memory");
}
execUserSetup()
{
__writeMemory32(0x0D3,0x98,"Register");
__message "-------------------------------Set PC ----------------------------------------";
__writeMemory32(0x00000000,0xB4,"Register");
}
/*********************************************************************
*
* _CheckNoRemap()
*
* Function description
* Check if Remap
*/
_CheckNoRemap() {
//* Read the value at 0x0
__mac_i =__readMemory32(0x00000000,"Memory");
__mac_mem = __mac_i;
__mac_i=__mac_i+1;
__writeMemory32(__mac_i,0x00,"Memory");
__mac_pt=__readMemory32(0x00000000,"Memory");
if (__mac_i == __mac_pt)
{
__message "------------------------------- The Remap is done ----------------------------------------";
__writeMemory32( __mac_mem,0x00000000,"Memory");
} else {
__message "------------------------------- The Remap is NOT -----------------------------------------";
//* Toggel RESET The remap
__writeMemory32(0x00000001,0xFFFFFF00,"Memory");
}
}
/*********************************************************************
*
* _PllSetting()
*
* Function description
* Set the PLL if need
*/
_PllSetting()
{
//* AT91F_LowLevelInit
//* Set Flash Waite sate
// Single Cycle Access at Up to 30 MHz, or 40
// if MCK = 47923200 I have 72 Cycle for 1 useconde ( flied MC_FMR->FMCN
__writeMemory32(0x00480100,0xFFFFFF60,"Memory");
// -1- Enabling the Main Oscillator:
//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600
// AT91C_CKGR_MOSCEN )); //0x0000 0001
__writeMemory32(0x00000601,0xFFFFFC20,"Memory");
// -2- Wait
// -3- Setting PLL and divider:
// - div by 5 Fin = 3,6864 =(18,432 / 5)
// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
// for 96 MHz the erroe is 0.16%
// Field out NOT USED = 0
// PLLCOUNT pll startup time esrtimate at : 0.844 ms
// PLLCOUNT 28 = 0.000844 /(1/32768)
// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x0E) | //0x0000 0005
// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00
// (AT91C_CKGR_MUL & (72<<16))); //0x0019 0000
__writeMemory32(0x00481C0E,0xFFFFFC2C,"Memory");
// -2- Wait
// -5- Selection of Master Clock and Processor Clock
// select the PLL clock divided by 2
// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003
// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004
__writeMemory32(0x00000007,0xFFFFFC30,"Memory");
__message " ---------------------------------------- PLL Set in improve time ";
}
/*********************************************************************
*
* _Chip_ID()
*
* Function description
* Read the Chip ID
*/
_Chip_ID() {
__mac_Trace = 0;
__mac_mem = 0;
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
__mac_i=__readMemory32(0xFFF00000,"Memory");
__message " ---------------------------------------- Chip ID Region 0xFFF00000 0x",__mac_i:%X;
if ( __mac_i == 0x14080044) { __mac_Trace++; __message " Chip ID for AT91M40800"; }
if ( __mac_i == 0x44000840) { __mac_Trace++; __message " Chip ID for AT91R40008"; }
if ( __mac_i == 0x14280041) { __mac_Trace++; __message " Chip ID for AT91M42800"; }
if ( __mac_i == 0x15580040) { __mac_Trace++; __message " Chip ID for AT91M55800"; }
__mac_i=__readMemory32(0xFF000004,"Memory");
__message " ---------------------------------------- Chip ID Region 0xFF000004 0x",__mac_i:%X;
if ( __mac_i == 0x00010221) { __mac_Trace++; __message " Chip ID for AT75C221 AT91C140"; }
__mac_i=__readMemory32(0xFFFFF240,"Memory");
__message " ---------------------------------------- Chip ID Region 0xFFFFF240 0x",__mac_i:%X;
if ( __mac_i == 0x034E0941) {__mac_Trace++; __message " Chip ID for AT91RM3400" ; }
if ( __mac_i == 0x09290781) {__mac_Trace++; __message " Chip ID for AT91RM9200" ; }
if ( __mac_i == 0x019703A0) {__mac_Trace++; __message " Chip ID for AT91SAM9261" ; }
if ( __mac_i == 0x27080340) {__mac_Trace++; __message " Chip ID for AT91SAM7S32" ; }
if ( __mac_i == 0x27080341) {__mac_Trace++; __message " Chip ID for AT91SAM7S32A" ; }
if ( __mac_i == 0x27080342) {__mac_Trace++; __message " Chip ID for AT91SAM7S321" ; }
if ( __mac_i == 0x27090540) {__mac_Trace++; __message " Chip ID for AT91SAM7S64 or AT91SAM7S64A" ;}
if ( __mac_i == 0x270C0740) {__mac_Trace++; __message " Chip ID for AT91SAM7S128" ; }
if ( __mac_i == 0x270A0741) {__mac_Trace++; __message " Chip ID for AT91SAM7S128A" ; }
if ( __mac_i == 0x270D0940) {__mac_Trace++; __message " Chip ID for AT91SAM7S256" ; }
if ( __mac_i == 0x270B0941) {__mac_Trace++; __message " Chip ID for AT91SAM7S256A" ; }
if ( __mac_i == 0x260A0941) {__mac_Trace++; __message " Chip ID for AT91SAM7A3 C" ; }
if ( __mac_i == 0x170A0940) {__mac_Trace++; __message " Chip ID for AT91SAM7A3 B" ; }
if ( __mac_i == 0x271A0740) { __mac_Trace++;__mac_mem=1; __message " Chip ID for AT91SAM7X128" ; }
if ( __mac_i == 0x271B0940) { __mac_Trace++;__mac_mem=1; __message " Chip ID for AT91SAM7X256" ; }
if ( __mac_i == 0x275A0740) { __mac_Trace++;__mac_mem=1; __message " Chip ID for AT91SAM7XC128" ; }
if ( __mac_i == 0x275B0940) { __mac_Trace++;__mac_mem=1; __message " Chip ID for AT91SAM7XC256" ; }
__mac_i=__readMemory32(0xFFFFEE40 ,"Memory");
__message " ---------------------------------------- Chip ID Region 0xFFFFEE40 0x",__mac_i:%X;
if ( __mac_i == 0x272A0940) {__mac_Trace++; __message " Chip ID for AT91SAM7SE256" ; }
if ( __mac_i == 0x272A0A40) {__mac_Trace++; __message " Chip ID for AT91SAM7SE512" ; }
if ( __mac_i == 0x019607A0) {__mac_Trace++; __message " Chip ID for AT91SAM9262" ; }
if ( __mac_i == 0x819607A0) {__mac_Trace++; __message " Chip ID for AT91SAM9263" ; }
if ( __mac_i == 0x019403A0) {__mac_Trace++; __message " Chip ID for AT91C340" ; }
if ( __mac_Trace == 0)
{
__message " unknown ID for AT91 device" ;
}
if ( __mac_Trace > 1)
{
__message " unknown ID for AT91 device" ;
__message " Chip ID ",__mac_Trace:%d;
}
}
/*********************************************************************
*
* _InitFlash()
*
* Function description
* Initializes the Flash time access (Memory controller).
* Set Flash Waite sate Single Cycle Access at Up to 30 MHz,
* if MCK = 47923200 I have 72 Cycle for 1 useconde (flied MC_FMR->FMCN)
* if MCK = 47923200 I have 48 Cycle for Non Volatile Memory Bits
*
*/
_InitFlash() {
// if ((AT91C_BASE_MC->MC_FSR & AT91C_MC_GPNVM2) == AT91C_MC_GPNVM2 )
if (__readMemory32(0xFFFFFF68,"Memory") & 0x400)
{
__message " ---------------------------------------- GPNVM 2 is already Set";
} else {
__writeMemory32(0x00300100,0xFFFFFF60,"Memory");
// AT91C_BASE_MC->MC_FCR = AT91C_MC_CORRECT_KEY | AT91C_MC_FCMD_SET_GP_NVM | (AT91C_MC_PAGEN & (gpnvm_bit << 8)) ;
__writeMemory32(0x5A00020B,0xFFFFFF64,"Memory");
__message " ---------------------------------------- SET GPNVM 2 ";
// while ((AT91C_BASE_MC->MC_FSR & AT91C_MC_FRDY) != AT91C_MC_FRDY ) {};
while( !(__readMemory32(0xFFFFFF68,"Memory") & 0x1) );
}
__writeMemory32(0x00480100,0xFFFFFF60,"Memory");
}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -