at91eb01.h

ARM7开发板 AT91EB01 BSP源代码

/* at91eb01.h - Atmel AT91M55800A header file */

/* Copyright 1999 ARM Limited */

/*
modification history
--------------------
12.23.2004  written.
*/

/*
This file contains I/O address and related constants for the Atmel AT91M55800A.
*/

#ifndef	INCat91eb01h
#define	INCat91eb01h

#define TARGET_AT91EB01


/*
 * Local-to-Bus memory address constants:
 * the local memory address always appears at 0 locally;
 * it is not dual ported.
 */

#define LOCAL_MEM_LOCAL_ADRS	0x00000000	  /* fixed */
#define LOCAL_MEM_BUS_ADRS	    0x00000000	  /* fixed */


#define BUS		                BUS_TYPE_NONE /* No PCI, VME etc. */


#define AT91EB01_MCLK_SPEED	    32000000	  /* MCLK speed, the timer */
						                      /* speed is related to this */

/*
 * Memory map
 * At reset, Flash ROM attached to CS0 is mapped to 0. We put a small
 * image into this Flash part to setup the EBI, cancel the boot mapping
 * and transfer control to the "proper" Bootrom image contained within
 * the Flash memory on the expansion card. Once the boot mapping has been
 * cancelled, the on-chip RAM is mapped to 0 upwards. The addresses of the
 * (off-chip) banks of memory below are programmed into the EBI.
 */

#define AT91_ON_CHIP_RAM_BASE_ADRS   	0
#define AT91_ON_CHIP_RAM_BANK_SIZE	    0x2000

#define AT91_ONBOARD_SRAM_BASE_ADRS	    0x02000000	/* where it is mapped */
#define AT91_ONBOARD_SRAM_BANK_SIZE	    0x00200000	/* on-main board SRAM */

#define AT91_ONBOARD_NVRAM_BASE_ADRS	0x40000000	/* where it is mapped */
#define AT91_ONBOARD_NVRAM_BANK_SIZE	0x00002000	/* on-main board NVRAM */

#define AT91EB01_OFF_CHIP_RAM_BASE_ADRS	0x02000000


/*
 * Flash ROMs: the power-up initialisation ROM (attached to CS0) is the
 * on-main-board Flash which initialises EBI and transfers control to our
 * "main" ROM on expansion card. It consists of two banks: the lower is
 * not writable, but the upper bank is writable. If the switch SW1 is set
 * to the UPPER MEM position, then the upper bank will appear in the
 * lower position as well, and we will be able to boot from that bank.
 *
 * The Expansion card Flash ROM is attached to CS2.
 */

#define AT91_ONBOARD_FLASH_BASE_ADRS		0x20000000
#define AT91_ONBOARD_FLASH_BANK_SIZE		0x00200000

#ifdef INCLUDE_FLASH

/* In either case, there is one two-byte-wide part */

#define FLASH_WIDTH	2

/*
 * Parameters to CPU delay loop needed by Flash memory driver: if
 * anything is changed to affect the performance of the board, then thse
 * will need recalibrating.  The values below are for a 25 MHz CPU, with
 * code running from SRAM.
 */

#define SYS_FLASH_BOARD_DELAY		/* use delay routine in sysLib.s */
#define SYS_FLASH_DELAY_SHIFT	0
#define SYS_FLASH_DELAY_ADJ	0
#define SYS_FLASH_DELAY_INCR	4

#endif /* INCLUDE_FLASH */


/*
 * Interrupt controller definitions
 * Note: FIQ is not handled within VxWorks so this is just IRQ
 */

#define AT91_AIC_BASE		0xFFFFF000	        /* Interrupt controller base */
#define AT91_AIC_SMR0	(AT91_AIC_BASE+0x000)   /* Source Mode reg (R/W) */
#define AT91_AIC_SVR0	(AT91_AIC_BASE+0x080)   /* Source Vector (R/W) */
#define AT91_AIC_IVR	(AT91_AIC_BASE+0x100)   /* IRQ Vector (R/O) */
#define AT91_AIC_FVR	(AT91_AIC_BASE+0x104)   /* FIQ Vector (R/O) */
#define AT91_AIC_ISR	(AT91_AIC_BASE+0x108)   /* Interrupt Source (R/O) */
#define AT91_AIC_IPR	(AT91_AIC_BASE+0x10C)   /* Interrupt Pending (R/O) */
#define AT91_AIC_IMR	(AT91_AIC_BASE+0x110)   /* Interrupt Mask (R/O) */
#define AT91_AIC_CISR	(AT91_AIC_BASE+0x114)   /* Core Interrupt Status (R/O)*/
#define AT91_AIC_IECR	(AT91_AIC_BASE+0x120)   /* Interrupt Enable Cmd (W/O) */
#define AT91_AIC_IDCR	(AT91_AIC_BASE+0x124)   /* Interrupt Disable Cmd (W/O)*/
#define AT91_AIC_ICCR	(AT91_AIC_BASE+0x128)   /* Interrupt Clear Cmd (W/O) */
#define AT91_AIC_ISCR	(AT91_AIC_BASE+0x12C)   /* Interrupt Set Cmd (W/O) */
#define AT91_AIC_EOICR	(AT91_AIC_BASE+0x130)   /* End of Interrupt Cmd (W/O) */
#define AT91_AIC_SPU	(AT91_AIC_BASE+0x134)   /* Spurious Vector (R/W) */


#define AT91_INT_POLARITY_NEGATIVE   (0 << 0)
#define AT91_INT_POLARITY_POSITIVE   (1 << 1)
#define AT91_INT_TYPE_EDGE           (1 << 0)
#define AT91_INT_TYPE_LEVEL          (0 << 0)

/*
 * We only need to include those we actually use i.e. we can currently
 * reduce to 6 (0 to 5 inclusive). If other interrupts are required
 * then this must be redefined appropriately.
 */

#define AT91_INT_NUM_LEVELS	30

/* definitions in form used by interrupt driver */

#define AT91_INT_CSR_MODE	AT91_AIC_SMR0	/* Source Mode register */
#define AT91_INT_CSR_SVEC	AT91_AIC_SVR0	/* Source Vector register */
#define AT91_INT_CSR_VECT	AT91_AIC_IVR	/* Interrupt vector register */
#define AT91_INT_CSR_PEND	AT91_AIC_IPR	/* Interrupt pending register */
#define AT91_INT_CSR_IMR	AT91_AIC_IMR	/* Interrupt Mask register */
#define AT91_INT_CSR_ENB	AT91_AIC_IECR	/* Interrupt Enable register */
#define AT91_INT_CSR_DIS	AT91_AIC_IDCR	/* Interrupt Disable register */
#define AT91_INT_CSR_EOIC	AT91_AIC_EOICR	/* End-ofInterrupt Command reg*/
#define AT91_INT_CSR_SPU	AT91_AIC_SPU	/* Spurious Vector register */


/* interrupt levels */

#define INT_LVL_SOFT		1	/* Software controllable interrupt */
#define INT_LVL_USART_0		2	/* USART 0 */
#define INT_LVL_USART_1		3	/* USART 1 */
#define INT_LVL_TIMER_0		6	/* Timer 0 */
#define INT_LVL_TIMER_1		7	/* Timer 1 */
#define INT_LVL_TIMER_2		8	/* Timer 2 */
#define INT_LVL_WDT	       	12	/* Watchdog timer */
#define INT_LVL_PIOA	    13	/* Parallel I/O */
#define INT_LVL_PIOB        14	/* Parallel I/O */
#define INT_LVL_EXT_0		29	/* External interrupt 0 */
#define INT_LVL_EXT_1		28	/* External interrupt 1 */
#define INT_LVL_EXT_2		27	/* External interrupt 2 */
#define INT_LVL_EXT_3		26	/* External interrupt 3 */
#define INT_LVL_EXT_4		25	/* External interrupt 4 */
#define INT_LVL_EXT_5		24	/* External interrupt 5 */


/* interrupt vectors */
#define INT_VEC_SOFT	   IVEC_TO_INUM(INT_LVL_SOFT)	    /* Soft interrupt */
#define INT_VEC_USART_0	   IVEC_TO_INUM(INT_LVL_USART_0)	/* USART 0 */
#define INT_VEC_USART_1	   IVEC_TO_INUM(INT_LVL_USART_1)	/* USART 1 */
#define INT_VEC_TIMER_0	   IVEC_TO_INUM(INT_LVL_TIMER_0)	/* Timer 0 */
#define INT_VEC_TIMER_1	   IVEC_TO_INUM(INT_LVL_TIMER_1)	/* Timer 1 */
#define INT_VEC_TIMER_2	   IVEC_TO_INUM(INT_LVL_TIMER_2)	/* Timer 2 */
#define INT_VEC_WDT	       IVEC_TO_INUM(INT_LVL_WDT)	    /* Watchdog timer */
#define INT_VEC_PIOA	   IVEC_TO_INUM(INT_LVL_PIOA)	    /* ParallelA I/O */
#define INT_VEC_PIOB	   IVEC_TO_INUM(INT_LVL_PIOB)	    /* ParallelB I/O */
#define INT_VEC_EXT_0	   IVEC_TO_INUM(INT_LVL_EXT_0)   	/* Ext. interrupt 0 */
#define INT_VEC_EXT_1	   IVEC_TO_INUM(INT_LVL_EXT_1)	    /* Ext. interrupt 1 */
#define INT_VEC_EXT_2	   IVEC_TO_INUM(INT_LVL_EXT_2)      /* Ext. interrupt 2 */
#define INT_VEC_EXT_3	   IVEC_TO_INUM(INT_LVL_EXT_3)      /* Ext. interrupt 3 */
#define INT_VEC_EXT_4	   IVEC_TO_INUM(INT_LVL_EXT_4)      /* Ext. interrupt 4 */
#define INT_VEC_EXT_5	   IVEC_TO_INUM(INT_LVL_EXT_5)      /* Ext. interrupt 5 */


/* definitions for SIO driver */

#ifdef INCLUDE_SERIAL
#define N_AT91_USART_CHANNELS	2
#else
#define N_AT91_USART_CHANNELS	0
#endif

#define N_SIO_CHANNELS		N_AT91_USART_CHANNELS
#define AT91_USART_FREQ		(AT91EB01_MCLK_SPEED)	/* clocked from MCKI */
#define AT91_USART_0_BASE_ADRS	0xFFFC0000	        /* USART 0 base address */
#define AT91_USART_1_BASE_ADRS	0xFFFC4000	        /* USART 1 base address */



/*
 * Definitions for the AT91 Timer: two timers clocked at same speed.
 * Otherwise use default definitions in at91Timer.h.
 */
#define SYS_TIMER_CLK   	(AT91EB01_MCLK_SPEED/128)	/* Frequency of C/T */
#define AUX_TIMER_CLK	    (AT91EB01_MCLK_SPEED/128)	/* Frequency of C/T */

#define SYS_TIMER_INT_LVL 	(INT_LVL_TIMER_0 + SYS_TIMER_NUM)
#define AUX_TIMER_INT_LVL 	(INT_LVL_TIMER_0 + AUX_TIMER_NUM)

#define SYS_TIMER_INT_VEC	IVEC_TO_INUM(SYS_TIMER_INT_LVL)
#define AUX_TIMER_INT_VEC	IVEC_TO_INUM(AUX_TIMER_INT_LVL)

/*
 * Clock rates depend upon CPU power and work load of application.
 * The values below are minimum and maximum allowed by the hardware.
 * Note that it has a 16-bit counter and we don't accept values that
 * would mean a zero reload value as we don't know what that will do.
 * So:
 * min frequency = roundup(clock_rate/(max_counter_value))
 * max frequency = rounddown(clock_rate/(min_counter_value))
 * i.e. SYS_CLK_RATE_MAX = SYS_TIMER_CLK
 *      AUX_CLK_RATE_MAX = AUX_TIMER_CLK
 *
 * However, we must set maxima that are sustainable on a running
 * system (determined by experimentation).
 *
 */

#define SYS_CLK_RATE_MIN ((SYS_TIMER_CLK+0xFFFF)/0x10000)
#define SYS_CLK_RATE_MAX 9000
#define AUX_CLK_RATE_MIN ((AUX_TIMER_CLK+0xFFFF)/0x10000)
#define AUX_CLK_RATE_MAX 9000


/* Watchdog timer */

#define AT91_WDT_OMR	0xFFFF8000	/* Overflow Mode Register */


/* Parallel I/O controller */
/* PIOA */
#define AT91_PIOA_PER	0xFFFEC000	/* PIOA Enable (W/O) */
#define AT91_PIOA_PDR	0xFFFEC004	/* PIOA Disable (W/O) */
#define AT91_PIOA_PSR	0xFFFEC008	/* PIOA Status (R/O) */
#define AT91_PIOA_OER	0xFFFEC010	/* Output Enable (W/O) */
#define AT91_PIOA_ODR	0xFFFEC014	/* Output Disable (W/O) */
#define AT91_PIOA_OSR	0xFFFEC018	/* Output Status (R/O) */
#define AT91_PIOA_SODR	0xFFFEC030	/* Set Output Data (W/O) */
#define AT91_PIOA_CODR	0xFFFEC034	/* Clear Output Data (W/O) */
#define AT91_PIOA_ODSR	0xFFFEC038	/* Output Data Status (R/O) */
#define AT91_PIOA_PDSR	0xFFFEC03C	/* Pin Data Status (R/O) */
#define AT91_PIOA_IER	0xFFFEC040	/* Interrupt Enable (W/O) */
#define AT91_PIOA_IDR	0xFFFEC044	/* Interrupt Disable (W/O) */
#define AT91_PIOA_IMR	0xFFFEC048	/* Interrupt Mask (R/O) */
#define AT91_PIOA_ISR	0xFFFEC04C	/* Interrupt Status (R/O) */

/* PIOB */
#define AT91_PIOB_PER	0xFFFF0000	/* PIOB Enable (W/O) */
#define AT91_PIOB_PDR	0xFFFF0004	/* PIOB Disable (W/O) */
#define AT91_PIOB_PSR	0xFFFF0008	/* PIOB Status (R/O) */
#define AT91_PIOB_OER	0xFFFF0010	/* Output Enable (W/O) */
#define AT91_PIOB_ODR	0xFFFF0014	/* Output Disable (W/O) */
#define AT91_PIOB_OSR	0xFFFF0018	/* Output Status (R/O) */
#define AT91_PIOB_SODR	0xFFFF0030	/* Set Output Data (W/O) */
#define AT91_PIOB_CODR	0xFFFF0034	/* Clear Output Data (W/O) */
#define AT91_PIOB_ODSR	0xFFFF0038	/* Output Data Status (R/O) */
#define AT91_PIOB_PDSR	0xFFFF003C	/* Pin Data Status (R/O) */
#define AT91_PIOB_IER	0xFFFF0040	/* Interrupt Enable (W/O) */
#define AT91_PIOB_IDR	0xFFFF0044	/* Interrupt Disable (W/O) */
#define AT91_PIOB_IMR	0xFFFF0048	/* Interrupt Mask (R/O) */
#define AT91_PIOB_ISR	0xFFFF004C	/* Interrupt Status (R/O) */


/* Special Function addresses */
#define AT91_SF_CIDR	0xFFF00000	/* Chip Id Register (R/O) */
#define AT91_SF_EXID	0xFFF00004	/* Chip Id Extension Register (R/O) */
#define AT91_SF_RSR	    0xFFF00008	/* Reset State Register (R/O) */
#define AT91_SF_PMR	    0xFFF00018	/* Protect Mode Register (R/W) */


#define AT91_PMR_KEY	(0x27A80 << 16)	/* Protect Mode Register key */
#define AT91_PMR_AIC	(1 << 5)


/* general purpose 32-bit register read/write macros */
#define AT91EB01_REG_READ(reg,val) ((val) = *(volatile UINT32 *)(reg))
#define AT91EB01_REG_WRITE(reg,val) (*(volatile UINT32 *)(reg) = (val))

#endif	/* INCat91eb01h */