📄 plx9056.h
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#define PLX9056_DMPBAM_RD_PFETCH_SZ_LSB_MASK 0x00000008
#define PLX9056_DMPBAM_RD_MODE_MASK 0x00000010
#define PLX9056_DMPBAM_ALMOST_FULL_FLAG_LSBS_MASK 0x000001e0
#define PLX9056_DMPBAM_WR_INVAL_MODE_MASK 0x00000200
#define PLX9056_DMPBAM_ALMOST_FULL_FLAG_MSB_MASK 0x00000400
#define PLX9056_DMPBAM_PFETCH_LIMIT_MASK 0x00000800
#define PLX9056_DMPBAM_RD_PFETCH_SZ_MSB_MASK 0x00001000
#define PLX9056_DMPBAM_IO_REMAP_SEL_MASK 0x00002000
#define PLX9056_DMPBAM_WR_DELAY_MASK 0x0000c000
#define PLX9056_DMPBAM_REMAP_VAL_MASK 0xffff0000
#define PLX9056_DMCFGA_REG (PLX_9056_ADDR + 0xAC)
#define PLX9056_DMCFGA_CONFIG_TYPE_MASK 0x00000003
#define PLX9056_DMCFGA_REG_NUM_MASK 0x000000fc
#define PLX9056_DMCFGA_FUNC_NUM_MASK 0x00000700
#define PLX9056_DMCFGA_DEV_NUM_MASK 0x0000f800
#define PLX9056_DMCFGA_BUS_NUM_MASK 0x00ff0000
#define PLX9056_DMCFGA_EN_MASK 0x80000000
#define PLX9056_OPLFIS_REG (PLX_9056_ADDR + 0xB0)
#define PLX9056_OPLFIS_INT_MASK 0x00000008
#define PLX9056_OPLFIM_REG (PLX_9056_ADDR + 0xB4)
#define PLX9056_OPLFIM_INT_MASK 0x00000008
#define PLX9056_MBOX0_REG (PLX_9056_ADDR + 0xC0)
#define PLX9056_MBOX1_REG (PLX_9056_ADDR + 0xC4)
#define PLX9056_MBOX2_REG (PLX_9056_ADDR + 0xC8)
#define PLX9056_MBOX3_REG (PLX_9056_ADDR + 0xCC)
#define PLX9056_MBOX4_REG (PLX_9056_ADDR + 0xD0)
#define PLX9056_MBOX5_REG (PLX_9056_ADDR + 0xD4)
#define PLX9056_MBOX6_REG (PLX_9056_ADDR + 0xD8)
#define PLX9056_MBOX7_REG (PLX_9056_ADDR + 0xDC)
#define PLX9056_P2LDBELL_REG (PLX_9056_ADDR + 0xE0)
#define PLX9056_L2PDBELL_REG (PLX_9056_ADDR + 0xE4)
#define PLX9056_INTCSR_REG (PLX_9056_ADDR + 0xE8)
#define PLX9056_INTCSR_LSERR_EN_MASK 0x00000001
#define PLX9056_INTCSR_LSERR_MODE_MASK 0x00000002
#define PLX9056_INTCSR_GEN_PCI_SERR_MASK 0x00000004
#define PLX9056_INTCSR_MBOX_INT_EN_MASK 0x00000008
#define PLX9056_INTCSR_PM_INT_EN_MASK 0x00000010
#define PLX9056_INTCSR_PM_INT_ACT_MASK 0x00000020
#define PLX9056_INTCSR_DMDS_PARCHK_EN_MASK 0x00000040
#define PLX9056_INTCSR_DMDS_PARCHK_ACT_MASK 0x00000080
#define PLX9056_INTCSR_PCI_INT_EN_MASK 0x00000100
#define PLX9056_INTCSR_PCI_DB_INT_EN_MASK 0x00000200
#define PLX9056_INTCSR_PCI_ABORT_INT_EN_MASK 0x00000400
#define PLX9056_INTCSR_PCI_LOCAL_INT_EN_MASK 0x00000800
#define PLX9056_INTCSR_RETRY_ABORT_EN_MASK 0x00001000
#define PLX9056_INTCSR_PCI_DB_INT_ACT_MASK 0x00002000
#define PLX9056_INTCSR_PCI_ABORT_INT_ACT_MASK 0x00004000
#define PLX9056_INTCSR_LINT_ACT_MASK 0x00008000
#define PLX9056_INTCSR_LINT_ENABLE_MASK 0x00010000
#define PLX9056_INTCSR_LOC_DB_INT_EN_MASK 0x00020000
#define PLX9056_INTCSR_LOC_DMA0_INT_EN_MASK 0x00040000
#define PLX9056_INTCSR_LOC_DMA1_INT_EN_MASK 0x00080000
#define PLX9056_INTCSR_LOC_DB_INT_ACT_MASK 0x00100000
#define PLX9056_INTCSR_LOC_DMA0_INT_ACT_MASK 0x00200000
#define PLX9056_INTCSR_LOC_DMA1_INT_ACT_MASK 0x00400000
#define PLX9056_INTCSR_BIST_INT_ACT_MASK 0x00800000
#define PLX9056_INTCSR_DIRECT_MSTR_ABORT_MASK 0x01000000
#define PLX9056_INTCSR_DMA0_MSTR_ABORT_MASK 0x02000000
#define PLX9056_INTCSR_DMA1_MSTR_ABORT_MASK 0x04000000
#define PLX9056_INTCSR_TOUT_MSTR_ABORT_MASK 0x08000000
#define PLX9056_INTCSR_MBOX_0_DATA_MASK 0x10000000
#define PLX9056_INTCSR_MBOX_1_DATA_MASK 0x20000000
#define PLX9056_INTCSR_MBOX_2_DATA_MASK 0x40000000
#define PLX9056_INTCSR_MBOX_3_DATA_MASK 0x80000000
#define PLX9056_CNTRL_REG (PLX_9056_ADDR + 0xEC)
#define PLX9056_CNTRL_DMA_RD_CMD_MASK 0x0000000f
#define PLX9056_CNTRL_DMA_WR_CMD_MASK 0x000000f0
#define PLX9056_CNTRL_DMA_WR_CMD_SHIFT 4
#define PLX9056_CNTRL_DMSTR_RD_CMD_MASK 0x00000f00
#define PLX9056_CNTRL_DMSTR_RD_CMD_SHIFT 8
#define PLX9056_CNTRL_DMSTR_WR_CMD_MASK 0x0000f000
#define PLX9056_CNTRL_DMSTR_WR_CMD_SHIFT 12
#define PLX9056_CNTRL_GPOUT_MASK 0x00010000
#define PLX9056_CNTRL_GPIN_MASK 0x00020000
#define PLX9056_CNTRL_USERIN_EN_MASK 0x00040000
#define PLX9056_CNTRL_USEROUT_EN_MASK 0x00080000
#define PLX9056_CNTRL_EE_CLK_MASK 0x01000000
#define PLX9056_CNTRL_EE_CS_MASK 0x02000000
#define PLX9056_CNTRL_EE_WR_BIT_MASK 0x04000000
#define PLX9056_CNTRL_EE_RD_BIT_MASK 0x08000000
#define PLX9056_CNTRL_EE_PRESENT_MASK 0x10000000
#define PLX9056_CNTRL_RELOAD_CFG_MASK 0x20000000
#define PLX9056_CNTRL_SW_RESET_MASK 0x40000000
#define PLX9056_PCIHIDR_REG (PLX_9056_ADDR + 0xF0)
#define PLX9056_PCIHIDR_VENID_MASK 0x0000ffff
#define PLX9056_PCIHIDR_DEVID_MASK 0xffff0000
#define PLX9056_PCIHREV_REG (PLX_9056_ADDR + 0xF4) /* 8 bits */
#define PLX9056_DMDAC_REG (PLX_9056_ADDR + 0x17C)
#define PLX9056_DMAMODE0_REG (PLX_9056_ADDR + 0x100)
#define PLX9056_DMAMODE0_LBWIDTH_MASK 0x00000003
#define PLX9056_DMAMODE0_WAIT_STATES_MASK 0x0000003c
#define PLX9056_DMAMODE0_RDY_IN_EN_MASK 0x00000040
#define PLX9056_DMAMODE0_BTERM_IN_EN_MASK 0x00000080
#define PLX9056_DMAMODE0_LBURST_EN_MASK 0x00000100
#define PLX9056_DMAMODE0_CHAINING_MASK 0x00000200
#define PLX9056_DMAMODE0_DONE_INT_EN_MASK 0x00000400
#define PLX9056_DMAMODE0_LADRS_MODE_MASK 0x00000800
#define PLX9056_DMAMODE0_DEMAND_MODE_MASK 0x00001000
#define PLX9056_DMAMODE0_WR_INVAL_MASK 0x00002000
#define PLX9056_DMAMODE0_EOT_EN_MASK 0x00004000
#define PLX9056_DMAMODE0_STP_XFER_MODE_MASK 0x00008000
#define PLX9056_DMAMODE0_CLR_CNT_MODE_MASK 0x00010000
#define PLX9056_DMAMODE0_INT_SEL_PCI_MASK 0x00020000
#define PLX9056_DMAPADR0_REG (PLX_9056_ADDR + 0x104)
#define PLX9056_DMALADR0_REG (PLX_9056_ADDR + 0x108)
#define PLX9056_DMASIZ0_REG (PLX_9056_ADDR + 0x10C)
#define PLX9056_DMADPR0_REG (PLX_9056_ADDR + 0x110)
#define PLX9056_DMADPR0_DESC_LOC_PCI_MASK 0x00000001
#define PLX9056_DMADPR0_END_CHAIN_MASK 0x00000002
#define PLX9056_DMADPR0_INT_AFTER_TC_MASK 0x00000004
#define PLX9056_DMADPR0_DIR_LOC2PCI_MASK 0x00000008
#define PLX9056_DMADPR0_NEXT_DESC_ADRS_MASK 0xfffffff0
#define PLX9056_DMAMODE1_REG (PLX_9056_ADDR + 0x114)
#define PLX9056_DMAMODE1_LBWIDTH_MASK 0x00000003
#define PLX9056_DMAMODE1_WAIT_STATES_MASK 0x0000003c
#define PLX9056_DMAMODE1_RDY_IN_EN_MASK 0x00000040
#define PLX9056_DMAMODE1_BTERM_IN_EN_MASK 0x00000080
#define PLX9056_DMAMODE1_LBURST_EN_MASK 0x00000100
#define PLX9056_DMAMODE1_CHAINING_MASK 0x00000200
#define PLX9056_DMAMODE1_DONE_INT_EN_MASK 0x00000400
#define PLX9056_DMAMODE1_LADRS_MODE_MASK 0x00000800
#define PLX9056_DMAMODE1_WR_INVAL_MASK 0x00002000
#define PLX9056_DMAMODE1_EOT_EN_MASK 0x00004000
#define PLX9056_DMAMODE1_STP_XFER_MODE_MASK 0x00008000
#define PLX9056_DMAMODE1_CLR_CNT_MODE_MASK 0x00010000
#define PLX9056_DMAMODE1_INT_SEL_PCI_MASK 0x00020000
#define PLX9056_DMAPADR1_REG (PLX_9056_ADDR + 0x118)
#define PLX9056_DMALADR1_REG (PLX_9056_ADDR + 0x11C)
#define PLX9056_DMASIZ1_REG (PLX_9056_ADDR + 0x120)
#define PLX9056_DMADPR1_REG (PLX_9056_ADDR + 0x124)
#define PLX9056_DMADPR1_DESC_LOC_PCI_MASK 0x00000001
#define PLX9056_DMADPR1_END_CHAIN_MASK 0x00000002
#define PLX9056_DMADPR1_INT_AFTER_TC_MASK 0x00000004
#define PLX9056_DMADPR1_DIR_LOC2PCI_MASK 0x00000008
#define PLX9056_DMADPR1_NEXT_DESC_ADRS_MASK 0xfffffff0
#define PLX9056_DMACSR0_REG (PLX_9056_ADDR + 0x128) /* 8 bits */
#define PLX9056_DMACSR0_ENABLE_MASK 0x01
#define PLX9056_DMACSR0_START_MASK 0x02
#define PLX9056_DMACSR0_ABORT_MASK 0x04
#define PLX9056_DMACSR0_CLR_INT_MASK 0x08
#define PLX9056_DMACSR0_DONE_MASK 0x10
#define PLX9056_DMACSR1_REG (PLX_9056_ADDR + 0x129) /* 8 bits */
#define PLX9056_DMACSR1_ENABLE_MASK 0x01
#define PLX9056_DMACSR1_START_MASK 0x02
#define PLX9056_DMACSR1_ABORT_MASK 0x04
#define PLX9056_DMACSR1_CLR_INT_MASK 0x08
#define PLX9056_DMACSR1_DONE_MASK 0x10
#define PLX9056_DMATHR_REG (PLX_9056_ADDR + 0x130)
#define PLX9056_DMATHR_C0PLAF_MASK 0x0000000f
#define PLX9056_DMATHR_C0LPAE_MASK 0x000000f0
#define PLX9056_DMATHR_C0LPAF_MASK 0x00000f00
#define PLX9056_DMATHR_C0PLAE_MASK 0x0000f000
#define PLX9056_DMATHR_C1PLAF_MASK 0x000f0000
#define PLX9056_DMATHR_C1LPAE_MASK 0x00f00000
#define PLX9056_DMATHR_C1LPAF_MASK 0x0f000000
#define PLX9056_DMATHR_C1PLAE_MASK 0xf0000000
#define PLX9056_DMADAC0_REG (PLX_9056_ADDR + 0x134)
#define PLX9056_DMADAC1_REG (PLX_9056_ADDR + 0x138)
#define PLX9056_MQCR_REG (PLX_9056_ADDR + 0x140)
#define PLX9056_MQCR_EN_MASK 0x00000001
#define PLX9056_MQCR_FIFO_SZ_MASK 0x0000003e
#define PLX9056_MQCR_FIFO_SZ_SHIFT 1
#define PLX9056_QBAR_REG (PLX_9056_ADDR + 0x144)
#define PLX9056_IFHPR_REG (PLX_9056_ADDR + 0x148)
#define PLX9056_IFHPR_FHP_MASK 0x000ffffc
#define PLX9056_IFHPR_QBA_MASK 0xfff00000
#define PLX9056_IFTPR_REG (PLX_9056_ADDR + 0x14C)
#define PLX9056_IFTPR_FTP_MASK 0x000ffffc
#define PLX9056_IFTPR_QBA_MASK 0xfff00000
#define PLX9056_IPHPR_REG (PLX_9056_ADDR + 0x150)
#define PLX9056_IPHPR_HP_MASK 0x000ffffc
#define PLX9056_IPHPR_QBA_MASK 0xfff00000
#define PLX9056_IPTPR_REG (PLX_9056_ADDR + 0x154)
#define PLX9056_IPTPR_TP_MASK 0x000ffffc
#define PLX9056_IPTPR_QBA_MASK 0xfff00000
#define PLX9056_OFHPR_REG (PLX_9056_ADDR + 0x158)
#define PLX9056_OFHPR_FHP_MASK 0x000ffffc
#define PLX9056_OFHPR_QBA_MASK 0xfff00000
#define PLX9056_OFTPR_REG (PLX_9056_ADDR + 0x15C)
#define PLX9056_OFTPR_FTP_MASK 0x000ffffc
#define PLX9056_OFTPR_QBA_MASK 0xfff00000
#define PLX9056_OPHPR_REG (PLX_9056_ADDR + 0x160)
#define PLX9056_OPHPR_HP_MASK 0x000ffffc
#define PLX9056_OPHPR_QBA_MASK 0xfff00000
#define PLX9056_OPTPR_REG (PLX_9056_ADDR + 0x164)
#define PLX9056_OPTPR_TP_MASK 0x000ffffc
#define PLX9056_OPTPR_QBA_MASK 0xfff00000
#define PLX9056_QSR_REG (PLX_9056_ADDR + 0x168)
#define PLX9056_QSR_I2O_EN_MASK 0x00000001
#define PLX9056_QSR_LOC_SP_SEL_MASK 0x00000002
#define PLX9056_QSR_OPLF_PFETCH_EN_MASK 0x00000004
#define PLX9056_QSR_IFLF_PFETCH_EN_MASK 0x00000008
#define PLX9056_QSR_IPLF_INT_MASK_MASK 0x00000010
#define PLX9056_QSR_IPLF_INTR_MASK 0x00000020
#define PLX9056_QSR_OFLF_OVF_INT_MASK_MASK 0x00000040
#define PLX9056_QSR_OFLF_OVF_INTR_MASK 0x00000080
#define PLX9056_LAS1RR_MEM_REG (PLX_9056_ADDR + 0x170)
#define PLX9056_LAS1RR_MEM_IO_MAPPED_MASK 0x00000001
#define PLX9056_LAS1RR_MEM_ADRS_SPACE_MASK 0x00000006
#define PLX9056_LAS1RR_MEM_PREFETCHABLE_READS_MASK 0x00000008
#define PLX9056_LAS1RR_MEM_ADRS_DECODE_MASK 0xfffffff0
#define PLX9056_LAS1RR_IO_REG (PLX_9056_ADDR + 0x170)
#define PLX9056_LAS1RR_IO_IO_MAPPED_MASK 0x00000001
#define PLX9056_LAS1RR_IO_ADRS_DECODE_MASK 0xfffffffc
#define PLX9056_LAS1BA_MEM_REG (PLX_9056_ADDR + 0x174)
#define PLX9056_LAS1BA_MEM_ENABLE_MASK 0x00000001
#define PLX9056_LAS1BA_MEM_LOCAL_ADRS_MASK 0xfffffff0
#define PLX9056_LAS1BA_IO_REG (PLX_9056_ADDR + 0x174)
#define PLX9056_LAS1BA_IO_ENABLE_MASK 0x00000001
#define PLX9056_LAS1BA_IO_LOCAL_ADRS_MASK 0xfffffffc
#define PLX9056_LBRD1_REG (PLX_9056_ADDR + 0x178)
#define PLX9056_LBRD1_MEM_BUS_WIDTH_MASK 0x00000003
#define PLX9056_LBRD1_MEM_WAIT_STATES_MASK 0x0000003c
#define PLX9056_LBRD1_MEM_WAIT_STATES_SHIFT 2
#define PLX9056_LBRD1_MEM_RDY_IN_ENABLE_MASK 0x00000040
#define PLX9056_LBRD1_MEM_BTERM_IN_EN_MASK 0x00000080
#define PLX9056_LBRD1_MEM_BURST_EN_MASK 0x00000100
#define PLX9056_LBRD1_MEM_PFETCH_DISABLE_MASK 0x00000200
#define PLX9056_LBRD1_RD_PFETCH_CNT_EN_MASK 0x00000400
#define PLX9056_LBRD1_PREFETCH_CNTR_MASK 0x00007800
#define PLX9056_LBRD1_PREFETCH_CNTR_SHIFT 11
#define PLX9056_PM_CAP_ID_REG (PLX_9056_ADDR + 0x180) /* 8 bits */
#define PLX9056_PM_NEXT_CAP_PTR_REG (PLX_9056_ADDR + 0x181) /* 8 bits */
#define PLX9056_PM_CAPS_REG (PLX_9056_ADDR + 0x182) /* 16 bits */
#define PLX9056_PM_CAPS_VER_MASK 0x0007
#define PLX9056_PM_CAPS_PCI_CLK_REQ_MASK 0x0008
#define PLX9056_PM_CAPS_AUX_PWR_SRC_MASK 0x0010
#define PLX9056_PM_CAPS_DSI_MASK 0x0020
#define PLX9056_PM_CAPS_D1_SUP_MASK 0x0200
#define PLX9056_PM_CAPS_D2_SUP_MASK 0x0400
#define PLX9056_PM_CAPS_PME_SUP_MASK 0x7800
#define PLX9056_PM_CS_REG (PLX_9056_ADDR + 0x184) /* 16 bits */
#define PLX9056_PM_CS_PWR_STATE_MASK 0x0003
#define PLX9056_PM_CS_PME_EN_MASK 0x0100
#define PLX9056_PM_CS_DATA_SEL_MASK 0x1e00
#define PLX9056_PM_CS_DATA_SCALE_MASK 0x6000
#define PLX9056_PM_CS_PME_STAT_MASK 0x8000
#define PLX9056_PMCSR_BRDG_REG (PLX_9056_ADDR + 0x186) /* 8 bits */
#define PLX9056_PM_DATA_REG (PLX_9056_ADDR + 0x187) /* 8 bits */
#define PLX9056_HS_CTRL_REG (PLX_9056_ADDR + 0x188) /* 8 bits */
#define PLX9056_HS_NEXT_CAP_PTR_REG (PLX_9056_ADDR + 0x189) /* 8 bits */
#define PLX9056_HS_CS_REG (PLX_9056_ADDR + 0x18A) /* 16 bits */
#define PLX9056_HS_CS_ENUM_INT_CLR_MASK 0x0002
#define PLX9056_HS_CS_ENUM_RMV_STAT_MASK 0x0040
#define PLX9056_HS_CS_ENUM_INS_STAT_MASK 0x0080
#define PLX9056_PCIARB_REG (PLX_9056_ADDR + 0x1A0)⌨️ 快捷键说明
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