plx9056.h

ARM7开发板 AT91EB01 BSP源代码

/*
Replace local address bits used in decode with the value specified here.
Bits above the 16 lsb's of value are written to PCI Remap Register for
Direct Master to PCI Memory at local offset 0xA8, bits 31..16.
*/
#define PCI_MSTR_ADRS_REMAP         (0x00000000)
/*
Assigns value to bits to use for decoding direct master to PCI Memory access.
Bits above the 16 lsb's of value are written to Local Base Address Register
for Direct Master to PCI Memory register at local offset 0xA0, bits 31..16.
*/
#define PCI_MSTR_MEM_BASE_ADRS      (0x40000000)
/*
Enable decode of direct master memory accesses.
Written to PCI Remap Register for Direct Master to PCI Memory
at local offset 0xA8, bit 0.
Must be 0 or 1.
*/
#define PCI_MSTR_MEM_ACCESS_EN      (1)
/*
Assigns value to bits to use for decoding direct master to PCI I/O
or Config access.
Bits above the 16 lsb's of value are written to Local Base Address Register
for Direct Master to PCI IO/CFG register at local offset 0xA4, bits 31..16.
*/
#define PCI_MSTR_IO_BASE_ADRS       (0x50000000)
/*
Enable decode of direct master I/O accesses.
Written to PCI Remap Register for Direct Master to PCI Memory
at local offset 0xA8, bit 1.
Must be 0 or 1.
*/
#define PCI_MSTR_IO_ACCESS_EN       (1)
/*
Number of local bus clock cycles before negating HOLD and releasing
local bus.
Written to Mode/Arbitration register at local offset 0x88, bits 7..0.
If nonzero, also sets bit 16 to enable timer.
Must be between 0 and 255.
*/
#define PCI_LOC_LTNCY_TMR           (0xc)
/*
Number of local bus clock cycles before reasserting HOLD after releasing
local bus.  Only applies to DMA operation.
Written to Mode/Arbitration register at local offset 0x88, bits 15..8.
If nonzero, also sets bit 17 to enable timer.
Must be between 0 and 255.
*/
#define PCI_LOC_PAUSE_TMR           (0)
/*
Use big-endian data ordering for local accesses to the configuration
registers.
Written to Big/Little Endian descriptor register at local offset 0x8C, bit 0.
Must be 0 or 1.
*/
#define PCI_CONFIG_BIG_END          (1)
/*
Use big-endian data ordering for direct master accesses.
Written to Big/Little Endian descriptor register at local offset 0x8C, bit 1.
Must be 0 or 1.
*/
#define PCI_DIRECT_MSTR_BIG_END     (0)
/*
Use big-endian data ordering for direct slave accesses to local
address space 0.
Written to Big/Little Endian descriptor register at local offset 0x8C, bit 2.
Must be 0 or 1.
*/
#define PCI_DIRECT_SLV0_BIG_END     (1)
/*
Use big-endian data ordering for direct slave accesses to local
address space 1.
Written to Big/Little Endian descriptor register at local offset 0x8C, bit 5.
Must be 0 or 1.
*/
#define PCI_DIRECT_SLV1_BIG_END     (1)
/*
Use big-endian data ordering for direct slave accesses to expansion ROM.
Written to Big/Little Endian descriptor register at local offset 0x8C, bit 3.
Must be 0 or 1.
*/
#define PCI_DIRECT_SLVROM_BIG_END   (0)
/*
In big-endian mode use byte lanes [31..16] for 16 bit local bus and [31..24]
for 8 bit.  If 0, use [15..0] and [7..0].
Written to Big/Little Endian descriptor register at local offset 0x8C, bit 4.
Must be 0 or 1.
*/
#define PCI_BIG_END_UPPER_BYTE_LN   (0)
/*
Use big-endian data ordering for DMA channel 0 accesses to local
address space.
Written to Big/Little Endian descriptor register at local offset 0x8C, bit 7.
Must be 0 or 1.
*/
#define PCI_DMA0_BIG_END            (0)
/*
Use big-endian data ordering for DMA channel 1 accesses to local
address space.
Written to Big/Little Endian descriptor register at local offset 0x8C, bit 6.
Must be 0 or 1.
*/
#define PCI_DMA1_BIG_END            (0)
/*
System cache line size in units of 32-bit words.
Written to PCI config regs at offset 0xC.
Must be between 0 and 255.
*/
#define PCI_CACHE_LINE_SIZE         (8)
/*
Units of PCI bus clocks that specify the amount of time the 9056 bus master
can burst data on the PCI bus.  Written to PCI config regs at offset 0xD.
Must be between 0 and 255.
*/
#define PCI_LATENCY_TIMER           (0x40)

/*
**
**
**
** 9056 register offsets and bit definitions
**
**
**
*/
#define PLX9056_PCIIDR_REG                     				(PLX_9056_ADDR + 0x0)

#define PLX9056_PCICR_REG            									(PLX_9056_ADDR + 0x04)
#define PLX9056_PCICR_STAT_MASK        								0xffff0000
#define PLX9056_PCICR_STAT_DPERR_MASK         				0x80000000
#define PLX9056_PCICR_STAT_SERR_MASK         					0x40000000
#define PLX9056_PCICR_STAT_RMABT_MASK         				0x20000000
#define PLX9056_PCICR_STAT_RTABT_MASK         				0x10000000
#define PLX9056_PCICR_STAT_STABT_MASK         				0x08000000
#define PLX9056_PCICR_STAT_DSELT_MASK         				0x06000000
#define PLX9056_PCICR_STAT_DATPAR_MASK         				0x01000000
#define PLX9056_PCICR_STAT_FASTBB_MASK         				0x00800000
#define PLX9056_PCICR_STAT_USER_MASK         					0x00400000
#define PLX9056_PCICR_STAT_CAPSTAT_MASK         			0x00100000
#define PLX9056_PCICR_CMD_MASK		        						0x0000ffff
#define PLX9056_PCICR_CMD_FASTBB_MASK         				0x00000200
#define PLX9056_PCICR_CMD_SERR_MASK         					0x00000100
#define PLX9056_PCICR_CMD_WAIT_MASK         					0x00000080
#define PLX9056_PCICR_CMD_PERR_MASK         					0x00000040
#define PLX9056_PCICR_CMD_VGAS_MASK         					0x00000020
#define PLX9056_PCICR_CMD_MEMWI_MASK         					0x00000010
#define PLX9056_PCICR_CMD_SPEC_MASK         					0x00000008
#define PLX9056_PCICR_CMD_BUSM_MASK         					0x00000004
#define PLX9056_PCICR_CMD_MEM_MASK         						0x00000002
#define PLX9056_PCICR_CMD_IO_MASK         						0x00000001

#define PLX9056_PCICONF_0C_REG           							(PLX_9056_ADDR + 0x0C)
#define PLX9056_PCICONF_0C_BIST_MASK         					0xff000000
#define PLX9056_PCICONF_0C_BIST_SUPP_MASK         		0x80000000
#define PLX9056_PCICONF_0C_BIST_START_MASK         		0x40000000
#define PLX9056_PCICONF_0C_BIST_STAT_MASK         		0x0f000000
#define PLX9056_PCICONF_0C_HDR_TYPE_MASK         			0x00ff0000
#define PLX9056_PCICONF_0C_MULTIFUNC_MASK         		0x00800000
#define PLX9056_PCICONF_0C_HDR_LAYOUT_MASK         		0x007f0000
#define PLX9056_PCICONF_0C_LATTIM_MASK         				0x0000ff00
#define PLX9056_PCICONF_0C_LATTIM_SHIFT        				8
#define PLX9056_PCICONF_0C_CACHE_LS_MASK         			0x000000ff

#define PLX9056_PCI_MEM_TO_REGS_REG                  	(PLX_9056_ADDR + 0x10)
#define PLX9056_PCI_MEM_TO_REGS_BASE_MASK          		0xffffff00

#define PLX9056_PCI_IO_TO_REGS_REG                   	(PLX_9056_ADDR + 0x14)
#define PLX9056_PCI_IO_TO_REGS_BASE_MASK          		0xffffff00

#define PLX9056_PCI_MEM_TO_LAS0_REG                  	(PLX_9056_ADDR + 0x18)
#define PLX9056_PCI_MEM_TO_LAS0_IO_MAPPED_MASK        0x00000001
#define PLX9056_PCI_MEM_TO_LAS0_ADRS_SPACE_MASK       0x00000006
#define PLX9056_PCI_MEM_TO_LAS0_PREFETCHABLE_MASK     0x00000008
#define PLX9056_PCI_MEM_TO_LAS0_BASE_ADRS_MASK        0xfffffff0

#define PLX9056_PCI_IO_TO_LAS0_REG                   	(PLX_9056_ADDR + 0x18)
#define PLX9056_PCI_IO_TO_LAS0_IO_MAPPED_MASK         0x00000001
#define PLX9056_PCI_IO_TO_LAS0_BASE_ADRS_MASK         0xfffffffc

#define PLX9056_PCI_MEM_TO_LAS1_REG                  	(PLX_9056_ADDR + 0x1C)
#define PLX9056_PCI_MEM_TO_LAS1_IO_MAPPED_MASK        0x00000001
#define PLX9056_PCI_MEM_TO_LAS1_ADRS_SPACE_MASK       0x00000006
#define PLX9056_PCI_MEM_TO_LAS1_PREFETCHABLE_MASK     0x00000008
#define PLX9056_PCI_MEM_TO_LAS1_BASE_ADRS_MASK        0xfffffff0

#define PLX9056_PCI_IO_TO_LAS1_REG                   	(PLX_9056_ADDR + 0x1C)
#define PLX9056_PCI_IO_TO_LAS1_IO_MAPPED_MASK         0x00000001
#define PLX9056_PCI_IO_TO_LAS1_BASE_ADRS_MASK         0xfffffffc

#define PLX9056_PCIERBAR_REG         									(PLX_9056_ADDR + 0x30)
#define PLX9056_PCIERBAR_EXPROM_ADR_MASK        			0xfffff800
#define PLX9056_PCIERBAR_EXPROM_EN_MASK         			0x00000001

#define PLX9056_NEW_CAP_PTR_REG      									(PLX_9056_ADDR + 0x34)
#define PLX9056_NEW_CAP_PTR_OFFSET_MASK	        			0x000000ff

#define PLX9056_LAS0RR_MEM_REG                       	(PLX_9056_ADDR + 0x80)
#define PLX9056_LAS0RR_MEM_IO_MAPPED_MASK         		0x00000001
#define PLX9056_LAS0RR_MEM_ADRS_SPACE_MASK           	0x00000006
#define PLX9056_LAS0RR_MEM_PREFETCHABLE_READS_MASK		0x00000008
#define PLX9056_LAS0RR_MEM_ADRS_DECODE_MASK           0xfffffff0

#define PLX9056_LAS0RR_IO_REG                        	(PLX_9056_ADDR + 0x80)
#define PLX9056_LAS0RR_IO_IO_MAPPED_MASK         			0x00000001
#define PLX9056_LAS0RR_IO_ADRS_DECODE_MASK          	0xfffffffc

#define PLX9056_LAS0BA_MEM_REG                       	(PLX_9056_ADDR + 0x84)
#define PLX9056_LAS0BA_MEM_ENABLE_MASK         				0x00000001
#define PLX9056_LAS0BA_MEM_LOCAL_ADRS_MASK            0xfffffff0

#define PLX9056_LAS0BA_IO_REG                        	(PLX_9056_ADDR + 0x84)
#define PLX9056_LAS0BA_IO_ENABLE_MASK         				0x00000001
#define PLX9056_LAS0BA_IO_LOCAL_ADRS_MASK          		0xfffffffc

#define PLX9056_MARBR_REG                     				(PLX_9056_ADDR + 0x88)
#define PLX9056_MARBR_LOC_LATENCY_TMR_MASK           	0x000000ff
#define PLX9056_MARBR_LOC_PAUSE_TMR_MASK           		0x0000ff00
#define PLX9056_MARBR_LOC_PAUSE_TMR_SHIFT           	8
#define PLX9056_MARBR_LOC_LATENCY_TMR_EN_MASK         0x00010000
#define PLX9056_MARBR_LOC_PAUSE_TMR_EN_MASK         	0x00020000
#define PLX9056_MARBR_LOC_BREQ_EN_MASK          			0x00040000
#define PLX9056_MARBR_DMA_PRIORITY_MASK           		0x00180000
#define PLX9056_MARBR_LOC_SLV_BUS_MODE_MASK         	0x00200000
#define PLX9056_MARBR_DIR_SLV_LLOCK_EN_MASK         	0x00400000
#define PLX9056_MARBR_PCI_REQ_MODE_MASK         			0x00800000
#define PLX9056_MARBR_PCI_V21_MODE_MASK         			0x01000000
#define PLX9056_MARBR_PCI_RD_NO_WR_MODE_MASK         	0x02000000
#define PLX9056_MARBR_PCI_RDWR_FLSH_MODE_MASK         0x04000000
#define PLX9056_MARBR_GATE_LOC_LAT_TMR_MASK         	0x08000000
#define PLX9056_MARBR_PCI_RD_NO_FLSH_MODE_MASK        0x10000000
#define PLX9056_MARBR_SEL_SUBSYSTEM_ID_MASK         	0x20000000
#define PLX9056_MARBR_DM_FIFO_ALMOST_FULL_MASK       	0x40000000

#define PLX9056_BIGEND_REG                     				(PLX_9056_ADDR + 0x8C)  /* 8 bits */
#define PLX9056_BIGEND_CONF_REG_BIG_MASK         			0x01
#define PLX9056_BIGEND_DIRECT_MSTR_BIG_MASK         	0x02
#define PLX9056_BIGEND_SLV_ADR_SPC_0_BIG_MASK         0x04
#define PLX9056_BIGEND_SLV_ADR_ROM_0_BIG_MASK         0x08
#define PLX9056_BIGEND_BIG_END_BYTE_LANE_MODE_MASK    0x10
#define PLX9056_BIGEND_SLV_ADR_SPC_1_BIG_MASK         0x20
#define PLX9056_BIGEND_DMA_CH_1_BIG_MASK         			0x40
#define PLX9056_BIGEND_DMA_CH_0_BIG_MASK         			0x80

#define PLX9056_LOC_MISC_REG			               			(PLX_9056_ADDR + 0x8D)  /* 8 bits */
#define PLX9056_LOC_MISC_BAR1_EN_MASK            			0x01
#define PLX9056_LOC_MISC_BAR1_SHIFT_MASK         			0x02
#define PLX9056_LOC_MISC_LOC_INIT_STAT_MASK         	0x04
#define PLX9056_LOC_MISC_DM_DELAY_MASK			         	0x10
#define PLX9056_LOC_MISC_TEA_INT_MASK_MASK			      0x20
#define PLX9056_LOC_MISC_DM_FIFO_RETRY_MASK			      0x40

#define PLX9056_EEPROM_WP_ADRS_REG               			(PLX_9056_ADDR + 0x8E)  /* 16 bits */

#define PLX9056_EROMRR_REG                     				(PLX_9056_ADDR + 0x90)

#define PLX9056_EROMBA_REG                     				(PLX_9056_ADDR + 0x94)
#define PLX9056_EROMBA_BREQO_DELAY_MASK            		0x0000000f
#define PLX9056_EROMBA_BREQO_ENABLE_MASK         			0x00000010
#define PLX9056_EROMBA_BREQO_TMR_RES_MASK         		0x00000020
#define PLX9056_EROMBA_VAL_MASK          							0xfffff800

#define PLX9056_LBRD0_REG                     				(PLX_9056_ADDR + 0x98)
#define PLX9056_LBRD0_MEM_BUS_WIDTH_MASK           		0x00000003
#define PLX9056_LBRD0_MEM_WAIT_STATES_MASK            0x0000003c
#define PLX9056_LBRD0_MEM_WAIT_STATES_SHIFT           2
#define PLX9056_LBRD0_MEM_RDY_IN_ENABLE_MASK         	0x00000040
#define PLX9056_LBRD0_MEM_BTERM_IN_EN_MASK         		0x00000080
#define PLX9056_LBRD0_MEM_PFETCH_DISABLE_MASK         0x00000100
#define PLX9056_LBRD0_ROM_PFETCH_DISABLE_MASK         0x00000200
#define PLX9056_LBRD0_RD_PFETCH_CNT_EN_MASK         	0x00000400
#define PLX9056_LBRD0_PREFETCH_CNTR_MASK            	0x00007800
#define PLX9056_LBRD0_PREFETCH_CNTR_SHIFT            	11
#define PLX9056_LBRD0_ROM_BUS_WIDTH_MASK           		0x00030000
#define PLX9056_LBRD0_ROM_BUS_WIDTH_SHIFT           	16
#define PLX9056_LBRD0_ROM_WAIT_STATES_MASK          	0x003c0000
#define PLX9056_LBRD0_ROM_WAIT_STATES_SHIFT          	18
#define PLX9056_LBRD0_ROM_RDY_IN_ENABLE_MASK         	0x00400000
#define PLX9056_LBRD0_ROM_BTERM_IN_EN_MASK         		0x00800000
#define PLX9056_LBRD0_MEM_BURST_EN_MASK         			0x01000000
#define PLX9056_LBRD0_PROM_LONG_LOAD_MASK         		0x02000000
#define PLX9056_LBRD0_ROM_BURST_EN_MASK         			0x04000000
#define PLX9056_LBRD0_SLV_PCI_WR_MODE_MASK         		0x08000000
#define PLX9056_LBRD0_TGT_RTRY_DELAY_MASK            	0xf0000000
#define PLX9056_LBRD0_TGT_RTRY_DELAY_SHIFT            28

#define PLX9056_DMRR_REG                     					(PLX_9056_ADDR + 0x9C)

#define PLX9056_DMLBAM_REG                     				(PLX_9056_ADDR + 0xA0)

#define PLX9056_DMLBAI_REG                     				(PLX_9056_ADDR + 0xA4)

#define PLX9056_DMPBAM_REG                     				(PLX_9056_ADDR + 0xA8)
#define PLX9056_DMPBAM_MEM_EN_MASK         						0x00000001
#define PLX9056_DMPBAM_IO_EN_MASK         						0x00000002
#define PLX9056_DMPBAM_LLOCK_IN_EN_MASK         			0x00000004