plx9056.h

ARM7开发板 AT91EB01 BSP源代码

/*
Defines the base address for accessing the registers of the 9056.
*/
#define PLX_9056_ADDR	0x60000000
/*
Defines the size of the address space used for the 9056 registers.
This is used in sysPhysMemDesc in sysLib.c to set up the MMU.
*/
#define PLX_9056_SIZE	0x8000

/*
MMU configuration for local access to PCI Memory Space and
PCI I/O Space.
The hardware is set up to map 256MB to each of these regions, but it
is generally not a good idea to map such large areas of memory
because of the memory consumed for page tables.
So, 1MB has been mapped to each of these regions.  If necessary,
the user should change these definitions to map whatever regions
are required.
Note that whatever is defined here must still be within the ranges
defined by PCI_MSTR_MEM_BASE_ADRS, PCI_MSTR_IO_BASE_ADRS, and
PCI_MSTR_ADRS_RANGE.
*/
#define LOCAL_TO_PCI_MEM_BASE	0x80000000
#define LOCAL_TO_PCI_MEM_SIZE	0x00100000
#define LOCAL_TO_PCI_IO_BASE	0x90000000
#define LOCAL_TO_PCI_IO_SIZE	0x00100000

/*
Defines the base address for accessing the internal registers of the 860.
This value is written to the Internal Memory Mapped Register (IMMR).
*/
#define PLX_IMMR_BASE 0xFF000000

/*
Specifies whether or not the 9056 registers which set PCI base addresses for PCI
accesses to local resources are initialized by the driver.  If chip is sitting on
a PCI bus that is initialized by either a BIOS or a PNP OS, this must be set to 0.
Otherwise, it must be set to 1.  If set to 0, the following elements of target data
will be ignored and do not need to be configured:
PCI_MEM_TO_REGS_BASE_ADRS
PCI_IO_TO_REGS_BASE_ADRS
PCI_LAS0_BASE_ADRS
PCI_LAS1_BASE_ADRS
*/
#define SET_PCI_TO_LOCAL_BASE_ADRS  (0)
/*
Defines the PCI Base Address for PCI Memory accesses to
9056 Local, Runtime, and DMA Registers.  All 32 bits must be specified.  Written to PCI Base
Address Register 0 at local offset 0x10.
The upper 24 bits are used.  Written to bits 31..8.
Unused bits are masked from the lsb end so the values must be left justified.
*/
#define PCI_MEM_TO_REGS_BASE_ADRS   (0)
/*
Defines the PCI Base Address for PCI I/O accesses to
9056 Local, Runtime, and DMA Registers.  All 32 bits must be specified.  Written to PCI Base
Address Register 1 at local offset 0x14.
The upper 24 bits are used.  Written to bits 31..8.
Unused bits are masked from the lsb end so the values must be left justified.
*/
#define PCI_IO_TO_REGS_BASE_ADRS    (0)
/*
Configures Local Address Space 0 to respond to PCI Memory accesses.
Writes a 0 to Local Address Space 0 Range Register at local offset 0x80, bit 0.
If set to 1, PCI_LAS0_IO must be 0.
*/
#define PCI_LAS0_MEM               (1)
/*
Configures Local Address Space 0 to respond to PCI I/O accesses.
Written to Local Address Space 0 Range Register at local offset 0x80, bit 0.
If set to 1, PCI_LAS0_MEM must be 0.
*/
#define PCI_LAS0_IO                (0)
/*
Defines which PCI address bits should be used for decoding PCI accesses to
Local Address Space 0.  All 32 bits must be specified.  Written to Local
Address Space 0 Range Register at local offset 0x80.
For IO, the upper 30 bits are used.  Written to bits 31..2.
For memory, the upper 28 bits are used.  Written to bits 31..4.
Unused bits are masked from the lsb end so the values must be left justified.
*/
#define PCI_LAS0_ADRS_DECODE       (0xff000000)
/*
Defines the PCI Base Address for accesses to
Local Address Space 0.  All 32 bits must be specified.  Written to PCI Base
Address Register 2 at local offset 0x18.
For IO, the upper 30 bits are used.  Written to bits 31..2.
For memory, the upper 28 bits are used.  Written to bits 31..4.
Unused bits are masked from the lsb end so the values must be left justified.
*/
#define PCI_LAS0_BASE_ADRS         (0)
/*
Local address bits to replace decoded PCI address bits.  All 32 bits must be
specified.  Written to Local Address Space 0 Remap Register at local offset 0x84.
For IO, the upper 30 bits are used.  Written to bits 31..2.
For memory, the upper 28 bits are used.  Written to bits 31..4.
Unused bits are masked from the lsb end so the values must be left justified.
*/
#define PCI_LAS0_ADRS_REMAP        (0)
/*
Bus width for Local Address Space 0.
0 = 8 bits, 1 = 16 bits, 2 or 3 = 32 bits.
Written to Local Address Space 0 / Expansion ROM Bus Region Descriptor
Register at local offset 0x98, bits 1..0.
*/
#define PCI_LAS0_BUS_WIDTH         (3)
/*
Number of internal wait states for Local Address Space 0.  Written to Local Address
Space 0 / Expansion ROM Bus Region Descriptor Register at local offset 0x98, bits 5..2.
Must be between 0 and 15.
*/
#define PCI_LAS0_WAIT_STATES       (0)
/*
Enables Ready input for Local Address Space 0.  Written to Local Address
Space 0 / Expansion ROM Bus Region Descriptor Register at local offset 0x98, bit 6.
Must be 0 or 1.
*/
#define PCI_LAS0_RDY_IN_EN         (1)
/*
Enables BTERM# input for Local Address Space 0.  Written to Local Address
Space 0 / Expansion ROM Bus Region Descriptor Register at local offset 0x98, bit 7.
Must be 0 or 1.
*/
#define PCI_LAS0_BTERM_IN_EN       (0)
/*
When 1 disables prefetch for Local Address Space 0.  Written to Local Address
Space 0 / Expansion ROM Bus Region Descriptor Register at local offset 0x98, bit 9.
Must be 0 or 1.
*/
#define PCI_LAS0_PREFETCH_DIS      (0)
/*
Enables prefetch count limit Local Address Space 0.  Written to Local Address
Space 0 / Expansion ROM Bus Region Descriptor Register at local offset 0x98, bit 10.
Must be 0 or 1.
*/
#define PCI_LAS0_RD_PFETCH_CNT_EN  (0)
/*
Prefetch count to set max number of lwords to prefetch during memory
read cycles for Local Address Space 0.  Written to Local Address
Space 0 / Expansion ROM Bus Region Descriptor Register at local offset 0x98, bits 14..11.
Must be between 0 and 15.
*/
#define PCI_LAS0_RD_PFETCH_COUNT   (0)
/*
Enables bursting for Local Address Space 0.  Written to Local Address
Space 0 / Expansion ROM Bus Region Descriptor Register at local offset 0x98, bit 8.
Must be 0 or 1.
*/
#define PCI_LAS0_BURST_EN          (1)
/*
Configures Local Address Space 1 to respond to PCI Memory accesses.
Writes a 0 to Local Address Space 1 Range Register at local offset 0x170, bit 0.
If set to 1, PCI_LAS1_IO must be 0.
*/
#define PCI_LAS1_MEM               (1)
/*
Configures Local Address Space 1 to respond to PCI I/O accesses.
Written to Local Address Space 1 Range Register at local offset 0x170, bit 0.
If set to 1, PCI_LAS1_MEM must be 0.
*/
#define PCI_LAS1_IO                (0)
/*
Defines which PCI address bits should be used for decoding PCI accesses to
Local Address Space 1.  All 32 bits must be specified.  Written to Local
Address Space 1 Range Register at local offset 0x170.
For IO, the upper 30 bits are used.  Written to bits 31..2.
For memory, the upper 28 bits are used.  Written to bits 31..4.
Unused bits are masked from the lsb end so the values must be left justified.
*/
#define PCI_LAS1_ADRS_DECODE       (0xff000000)
/*
Defines the PCI Base Address for accesses to
Local Address Space 1.  All 32 bits must be specified.  Written to PCI Base
Address Register 3 at local offset 0x1C.
For IO, the upper 30 bits are used.  Written to bits 31..2.
For memory, the upper 28 bits are used.  Written to bits 31..4.
Unused bits are masked from the lsb end so the values must be left justified.
*/
#define PCI_LAS1_BASE_ADRS         (0)
/*
Local address bits to replace decoded PCI address bits.  All 32 bits must be
specified.  Written to Local Address Space 1 Remap Register at local offset 0x174.
For IO, the upper 30 bits are used.  Written to bits 31..2.
For memory, the upper 28 bits are used.  Written to bits 31..4.
Unused bits are masked from the lsb end so the values must be left justified.
*/
#define PCI_LAS1_ADRS_REMAP        (0x00000000)
/*
Bus width for Local Address Space 1.
0 = 8 bits, 1 = 16 bits, 2 or 3 = 32 bits.
Written to Local Address Space 1 Region Descriptor
Register at local offset 0x178, bits 1..0.
*/
#define PCI_LAS1_BUS_WIDTH         (3)
/*
Number of internal wait states for Local Address Space 1.  Written to Local Address
Space 1 Region Descriptor Register at local offset 0x178, bits 5..2.
Must be between 0 and 15.
*/
#define PCI_LAS1_WAIT_STATES       (0)
/*
Enables Ready input for Local Address Space 1.  Written to Local Address
Space 1 Region Descriptor Register at local offset 0x178, bit 6.
Must be 0 or 1.
*/
#define PCI_LAS1_RDY_IN_EN         (1)
/*
Enables BTERM# input for Local Address Space 1.  Written to Local Address
Space 1 Region Descriptor Register at local offset 0x178, bit 7.
Must be 0 or 1.
*/
#define PCI_LAS1_BTERM_IN_EN       (0)
/*
When 1 disables prefetch for Local Address Space 1.  Written to Local Address
Space 1 Region Descriptor Register at local offset 0x178, bit 9.
Must be 0 or 1.
*/
#define PCI_LAS1_PREFETCH_DIS      (0)
/*
Enables prefetch count limit Local Address Space 1.  Written to Local Address
Space 1 Region Descriptor Register at local offset 0x178, bit 10.
Must be 0 or 1.
*/
#define PCI_LAS1_RD_PFETCH_CNT_EN  (0)
/*
Prefetch count to set max number of lwords to prefetch during memory
read cycles for Local Address Space 1.  Written to Local Address
Space 1 Region Descriptor Register at local offset 0x178, bits 14..11.
Must be between 0 and 15.
*/
#define PCI_LAS1_RD_PFETCH_COUNT   (0)
/*
Enables bursting for Local Address Space 1.  Written to Local Address
Space 1 Region Descriptor Register at local offset 0x178, bit 8.
Must be 0 or 1.
*/
#define PCI_LAS1_BURST_EN          (1)
/*
Defines which PCI address bits should be used for decoding PCI to
local bus expansion ROM accesses.
Bits above the 11 lsb's of value are written to Expansion ROM Range Register
at local offset 0x90, bits 31..11.
*/
#define PCI_EXP_ROM_ADRS_RANGE      (0x00000000)
/*
Replace PCI address bits used in decode with the value specified here.
Bits above the 11 lsb's of value are written to the Expansion ROM Remap
Register at local offset 0x94, bits 31..11.
*/
#define PCI_EXP_ROM_ADRS_REMAP      (0x00000000)
/*
When 1 disables prefetching for Expansion ROM space.  Written to Local Address
Space 0 / Expansion ROM Bus Region Descriptor Register at local offset 0x98, bit 9.
Must be 0 or 1.
*/
#define PCI_EXP_ROM_PREFETCH_DIS    (0)
/*
Bus width for Expansion ROM space.
0 = 8 bits, 1 = 16 bits, 2 or 3 = 32 bits.
Written to Local Address Space 0 / Expansion ROM Bus Region Descriptor
Register at local offset 0x98, bits 17..16.
*/
#define PCI_EXP_ROM_BUS_WIDTH       (2)
/*
Number of internal wait states for Expansion ROM space.  Written to Local Address
Space 0 / Expansion ROM Bus Region Descriptor Register at local offset 0x98, bits 21..18.
Must be between 0 and 15.
*/
#define PCI_EXP_ROM_WAIT_STATES     (0)
/*
Enables Ready input for Expansion ROM space.  Written to Local Address
Space 0 / Expansion ROM Bus Region Descriptor Register at local offset 0x98, bit 22.
Must be 0 or 1.
*/
#define PCI_EXP_ROM_RDY_IN_EN       (1)
/*
Enables BTERM# input for Expansion ROM space.  Written to Local Address
Space 0 / Expansion ROM Bus Region Descriptor Register at local offset 0x98, bit 23.
Must be 0 or 1.
*/
#define PCI_EXP_ROM_BTERM_IN_EN     (0)
/*
Enables bursting for the Expansion ROM space.  Written to Local Address
Space 0 / Expansion ROM Bus Region Descriptor Register at local offset 0x98, bit 26.
Must be 0 or 1.
*/
#define PCI_EXP_ROM_BURST_EN        (0)
/*
Defines which local address bits should be used for decoding direct master
to PCI accesses (memory, I/O, and config).
Bits above the 16 lsb's of value are written to Local Range Register
for Direct Master to PCI register at local offset 0x9C, bits 31..16.
*/
#define PCI_MSTR_ADRS_RANGE         (0xfff00000)