ops2.c

BIOS emulator and interface to Realmode X86 Emulator Library Can emulate a PCI Graphic Controller V

    u16 *srcreg;

    START_OF_INSTR();
    DECODE_PRINTF("MOVZX\t");
    FETCH_DECODE_MODRM(mod, rh, rl);
    switch (mod) {
    case 0:
        destreg = DECODE_RM_LONG_REGISTER(rh);
        DECODE_PRINTF(",");
        srcoffset = decode_rm00_address(rl);
        srcval = fetch_data_word(srcoffset);
        DECODE_PRINTF("\n");
        TRACE_AND_STEP();
        *destreg = srcval;
        break;
    case 1:
        destreg = DECODE_RM_LONG_REGISTER(rh);
        DECODE_PRINTF(",");
        srcoffset = decode_rm01_address(rl);
        srcval = fetch_data_word(srcoffset);
        DECODE_PRINTF("\n");
        TRACE_AND_STEP();
        *destreg = srcval;
        break;
    case 2:
        destreg = DECODE_RM_LONG_REGISTER(rh);
        DECODE_PRINTF(",");
        srcoffset = decode_rm10_address(rl);
        srcval = fetch_data_word(srcoffset);
        DECODE_PRINTF("\n");
        TRACE_AND_STEP();
        *destreg = srcval;
        break;
    case 3:                     /* register to register */
        destreg = DECODE_RM_LONG_REGISTER(rh);
        DECODE_PRINTF(",");
        srcreg = DECODE_RM_WORD_REGISTER(rl);
        DECODE_PRINTF("\n");
        TRACE_AND_STEP();
        *destreg = *srcreg;
        break;
    }
    DECODE_CLEAR_SEGOVR();
    END_OF_INSTR();
}

/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xbb
****************************************************************************/
void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2))
{
    int mod, rl, rh;
    uint srcoffset;
    int bit,disp;

    START_OF_INSTR();
    DECODE_PRINTF("BTC\t");
    FETCH_DECODE_MODRM(mod, rh, rl);
    switch (mod) {
    case 0:
        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
            u32 srcval,mask;
            u32 *shiftreg;

            srcoffset = decode_rm00_address(rl);
            DECODE_PRINTF(",");
            shiftreg = DECODE_RM_LONG_REGISTER(rh);
            TRACE_AND_STEP();
            bit = *shiftreg & 0x1F;
            disp = (s16)*shiftreg >> 5;
            srcval = fetch_data_long(srcoffset+disp);
            mask = (0x1 << bit);
            CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
            store_data_long(srcoffset+disp, srcval ^ mask);
        } else {
            u16 srcval,mask;
            u16 *shiftreg;

            srcoffset = decode_rm00_address(rl);
            DECODE_PRINTF(",");
            shiftreg = DECODE_RM_WORD_REGISTER(rh);
            TRACE_AND_STEP();
            bit = *shiftreg & 0xF;
            disp = (s16)*shiftreg >> 4;
            srcval = fetch_data_word(srcoffset+disp);
			mask = (u16)(0x1 << bit);
            CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
			store_data_word(srcoffset+disp, (u16)(srcval ^ mask));
        }
        break;
    case 1:
        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
            u32 srcval,mask;
            u32 *shiftreg;

            srcoffset = decode_rm01_address(rl);
            DECODE_PRINTF(",");
            shiftreg = DECODE_RM_LONG_REGISTER(rh);
            TRACE_AND_STEP();
            bit = *shiftreg & 0x1F;
            disp = (s16)*shiftreg >> 5;
            srcval = fetch_data_long(srcoffset+disp);
            mask = (0x1 << bit);
            CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
            store_data_long(srcoffset+disp, srcval ^ mask);
        } else {
            u16 srcval,mask;
            u16 *shiftreg;

            srcoffset = decode_rm01_address(rl);
            DECODE_PRINTF(",");
            shiftreg = DECODE_RM_WORD_REGISTER(rh);
            TRACE_AND_STEP();
            bit = *shiftreg & 0xF;
            disp = (s16)*shiftreg >> 4;
            srcval = fetch_data_word(srcoffset+disp);
			mask = (u16)(0x1 << bit);
			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
			store_data_word(srcoffset+disp, (u16)(srcval ^ mask));
        }
        break;
    case 2:
        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
            u32 srcval,mask;
            u32 *shiftreg;

            srcoffset = decode_rm10_address(rl);
            DECODE_PRINTF(",");
            shiftreg = DECODE_RM_LONG_REGISTER(rh);
            TRACE_AND_STEP();
            bit = *shiftreg & 0x1F;
            disp = (s16)*shiftreg >> 5;
            srcval = fetch_data_long(srcoffset+disp);
            mask = (0x1 << bit);
            CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
            store_data_long(srcoffset+disp, srcval ^ mask);
        } else {
            u16 srcval,mask;
            u16 *shiftreg;

            srcoffset = decode_rm10_address(rl);
            DECODE_PRINTF(",");
            shiftreg = DECODE_RM_WORD_REGISTER(rh);
            TRACE_AND_STEP();
            bit = *shiftreg & 0xF;
            disp = (s16)*shiftreg >> 4;
            srcval = fetch_data_word(srcoffset+disp);
			mask = (u16)(0x1 << bit);
			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
			store_data_word(srcoffset+disp, (u16)(srcval ^ mask));
        }
        break;
    case 3:                     /* register to register */
        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
			u32 *srcreg,*shiftreg;
            u32 mask;

            srcreg = DECODE_RM_LONG_REGISTER(rl);
            DECODE_PRINTF(",");
            shiftreg = DECODE_RM_LONG_REGISTER(rh);
            TRACE_AND_STEP();
            bit = *shiftreg & 0x1F;
            mask = (0x1 << bit);
			CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
			*srcreg ^= mask;
		} else {
			u16 *srcreg,*shiftreg;
			u16 mask;

			srcreg = DECODE_RM_WORD_REGISTER(rl);
			DECODE_PRINTF(",");
			shiftreg = DECODE_RM_WORD_REGISTER(rh);
			TRACE_AND_STEP();
			bit = *shiftreg & 0xF;
			mask = (u16)(0x1 << bit);
            CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
            *srcreg ^= mask;
        }
        break;
    }
    DECODE_CLEAR_SEGOVR();
    END_OF_INSTR();
}

/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xbe
****************************************************************************/
void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2))
{
    int mod, rl, rh;
    uint srcoffset;

    START_OF_INSTR();
    DECODE_PRINTF("MOVSX\t");
    FETCH_DECODE_MODRM(mod, rh, rl);
    switch (mod) {
    case 0:
        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
            u32 *destreg;
            u32 srcval;

            destreg = DECODE_RM_LONG_REGISTER(rh);
            DECODE_PRINTF(",");
            srcoffset = decode_rm00_address(rl);
            srcval = (s32)((s8)fetch_data_byte(srcoffset));
            DECODE_PRINTF("\n");
            TRACE_AND_STEP();
            *destreg = srcval;
        } else {
            u16 *destreg;
            u16 srcval;

            destreg = DECODE_RM_WORD_REGISTER(rh);
            DECODE_PRINTF(",");
            srcoffset = decode_rm00_address(rl);
            srcval = (s16)((s8)fetch_data_byte(srcoffset));
            DECODE_PRINTF("\n");
            TRACE_AND_STEP();
            *destreg = srcval;
        }
        break;
    case 1:
        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
            u32 *destreg;
            u32 srcval;

            destreg = DECODE_RM_LONG_REGISTER(rh);
            DECODE_PRINTF(",");
            srcoffset = decode_rm01_address(rl);
            srcval = (s32)((s8)fetch_data_byte(srcoffset));
            DECODE_PRINTF("\n");
            TRACE_AND_STEP();
            *destreg = srcval;
        } else {
            u16 *destreg;
            u16 srcval;

            destreg = DECODE_RM_WORD_REGISTER(rh);
            DECODE_PRINTF(",");
            srcoffset = decode_rm01_address(rl);
            srcval = (s16)((s8)fetch_data_byte(srcoffset));
            DECODE_PRINTF("\n");
            TRACE_AND_STEP();
            *destreg = srcval;
        }
        break;
    case 2:
        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
            u32 *destreg;
            u32 srcval;

            destreg = DECODE_RM_LONG_REGISTER(rh);
            DECODE_PRINTF(",");
            srcoffset = decode_rm10_address(rl);
            srcval = (s32)((s8)fetch_data_byte(srcoffset));
            DECODE_PRINTF("\n");
            TRACE_AND_STEP();
            *destreg = srcval;
        } else {
            u16 *destreg;
            u16 srcval;

            destreg = DECODE_RM_WORD_REGISTER(rh);
            DECODE_PRINTF(",");
            srcoffset = decode_rm10_address(rl);
            srcval = (s16)((s8)fetch_data_byte(srcoffset));
            DECODE_PRINTF("\n");
            TRACE_AND_STEP();
            *destreg = srcval;
        }
        break;
    case 3:                     /* register to register */
        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
            u32 *destreg;
            u8  *srcreg;

            destreg = DECODE_RM_LONG_REGISTER(rh);
            DECODE_PRINTF(",");
            srcreg = DECODE_RM_BYTE_REGISTER(rl);
            DECODE_PRINTF("\n");
            TRACE_AND_STEP();
            *destreg = (s32)((s8)*srcreg);
        } else {
            u16 *destreg;
            u8  *srcreg;

            destreg = DECODE_RM_WORD_REGISTER(rh);
            DECODE_PRINTF(",");
            srcreg = DECODE_RM_BYTE_REGISTER(rl);
            DECODE_PRINTF("\n");
            TRACE_AND_STEP();
            *destreg = (s16)((s8)*srcreg);
        }
        break;
    }
    DECODE_CLEAR_SEGOVR();
    END_OF_INSTR();
}

/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xbf
****************************************************************************/
void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2))
{
    int mod, rl, rh;
    uint srcoffset;
    u32 *destreg;
    u32 srcval;
    u16 *srcreg;

    START_OF_INSTR();
    DECODE_PRINTF("MOVSX\t");
    FETCH_DECODE_MODRM(mod, rh, rl);
    switch (mod) {
    case 0:
        destreg = DECODE_RM_LONG_REGISTER(rh);
        DECODE_PRINTF(",");
        srcoffset = decode_rm00_address(rl);
        srcval = (s32)((s16)fetch_data_word(srcoffset));
        DECODE_PRINTF("\n");
        TRACE_AND_STEP();
        *destreg = srcval;
        break;
    case 1:
        destreg = DECODE_RM_LONG_REGISTER(rh);
        DECODE_PRINTF(",");
        srcoffset = decode_rm01_address(rl);
        srcval = (s32)((s16)fetch_data_word(srcoffset));
        DECODE_PRINTF("\n");
        TRACE_AND_STEP();
        *destreg = srcval;
        break;
    case 2:
        destreg = DECODE_RM_LONG_REGISTER(rh);
        DECODE_PRINTF(",");
        srcoffset = decode_rm10_address(rl);
        srcval = (s32)((s16)fetch_data_word(srcoffset));
        DECODE_PRINTF("\n");
        TRACE_AND_STEP();
        *destreg = srcval;
        break;
    case 3:                     /* register to register */
        destreg = DECODE_RM_LONG_REGISTER(rh);
        DECODE_PRINTF(",");
        srcreg = DECODE_RM_WORD_REGISTER(rl);
        DECODE_PRINTF("\n");
        TRACE_AND_STEP();
        *destreg = (s32)((s16)*srcreg);
        break;
    }
    DECODE_CLEAR_SEGOVR();
    END_OF_INSTR();
}

/***************************************************************************
 * Double byte operation code table:
 **************************************************************************/
void (*x86emu_optab2[256])(u8) =
{
/*  0x00 */ x86emuOp2_illegal_op,  /* Group F (ring 0 PM)      */
/*  0x01 */ x86emuOp2_illegal_op,  /* Group G (ring 0 PM)      */
/*  0x02 */ x86emuOp2_illegal_op,  /* lar (ring 0 PM)          */
/*  0x03 */ x86emuOp2_illegal_op,  /* lsl (ring 0 PM)          */
/*  0x04 */ x86emuOp2_illegal_op,
/*  0x05 */ x86emuOp2_illegal_op,  /* loadall (undocumented)   */
/*  0x06 */ x86emuOp2_illegal_op,  /* clts (ring 0 PM)         */
/*  0x07 */ x86emuOp2_illegal_op,  /* loadall (undocumented)   */
/*  0x08 */ x86emuOp2_illegal_op,  /* invd (ring 0 PM)         */
/*  0x09 */ x86emuOp2_illegal_op,  /* wbinvd (ring 0 PM)       */
/*  0x0a */ x86emuOp2_illegal_op,
/*  0x0b */ x86emuOp2_illegal_op,
/*  0x0c */ x86emuOp2_illegal_op,
/*  0x0d */ x86emuOp2_illegal_op,
/*  0x0e */ x86emuOp2_illegal_op,
/*  0x0f */ x86emuOp2_illegal_op,

/*  0x10 */ x86emuOp2_illegal_op,
/*  0x11 */ x86emuOp2_illegal_op,
/*  0x12 */ x86emuOp2_illegal_op,
/*  0x13 */ x86emuOp2_illegal_op,
/*  0x14 */ x86emuOp2_illegal_op,
/*  0x15 */ x86emuOp2_illegal_op,
/*  0x16 */ x86emuOp2_illegal_op,
/*  0x17 */ x86emuOp2_illegal_op,
/*  0x18 */ x86emuOp2_illegal_op,
/*  0x19 */ x86emuOp2_illegal_op,
/*  0x1a */ x86emuOp2_illegal_op,
/*  0x1b */ x86emuOp2_illegal_op,
/*  0x1c */ x86emuOp2_illegal_op,
/*  0x1d */ x86emuOp2_illegal_op,
/*  0x1e */ x86emuOp2_illegal_op,
/*  0x1f */ x86emuOp2_illegal_op,

/*  0x20 */ x86emuOp2_illegal_op,  /* mov reg32,creg (ring 0 PM) */
/*  0x21 */ x86emuOp2_illegal_op,  /* mov reg32,dreg (ring 0 PM) */
/*  0x22 */ x86emuOp2_illegal_op,  /* mov creg,reg32 (ring 0 PM) */
/*  0x23 */ x86emuOp2_illegal_op,  /* mov dreg,reg32 (ring 0 PM) */
/*  0x24 */ x86emuOp2_illegal_op,  /* mov reg32,treg (ring 0 PM) */
/*  0x25 */ x86emuOp2_illegal_op,
/*  0x26 */ x86emuOp2_illegal_op,  /* mov treg,reg32 (ring 0 PM) */
/*  0x27 */ x86emuOp2_illegal_op,
/*  0x28 */ x86emuOp2_illegal_op,
/*  0x29 */ x86emuOp2_illegal_op,
/*  0x2a */ x86emuOp2_illegal_op,
/*  0x2b */ x86emuOp2_illegal_op,
/*  0x2c */ x86emuOp2_illegal_op,
/*  0x2d */ x86emuOp2_illegal_op,
/*  0x2e */ x86emuOp2_illegal_op,
/*  0x2f */ x86emuOp2_illegal_op,

/*  0x30 */ x86emuOp2_illegal_op,
/*  0x31 */ x86emuOp2_illegal_op,
/*  0x32 */ x86emuOp2_illegal_op,
/*  0x33 */ x86emuOp2_illegal_op,
/*  0x34 */ x86emuOp2_illegal_op,
/*  0x35 */ x86emuOp2_illegal_op,
/*  0x36 */ x86emuOp2