laczipmixer\mc9s12d64equ.inc

freescale的资料

EDIV4:      equ   %00010000   ;clock divider bit
EDIV3:      equ   %00001000   ;clock divider bit
EDIV2:      equ   %00000100   ;clock divider bit
EDIV1:      equ   %00000010   ;clock divider bit
EDIV0:      equ   %00000001   ;clock divider bit

; $111 reserved

; $112 reserved 

ECNFG:      equ   $113        ;EEPROM configuration register
;
ECBEIE:     equ   %10000000   ;command buffer empty INT enable
ECCIE:      equ   %01000000   ;command complete interrupt enable

EPROT:      equ   $114        ;EEPROM protection register
;
EPOPEN:     equ   %10000000   ;opens EEPROM for program or erase
ENV6:       equ   %01000000   ;non volatile flag bit
ENV5:       equ   %00100000   ;non volatile flag bit
ENV4:       equ   %00010000   ;non volatile flag bit
EPDIS:      equ   %00001000   ;EEPROM protect addr rnge disable
EP2:        equ   %00000100   ;EEPROM protection address size
EP1:        equ   %00000010   ;EEPROM protection address size
EP0:        equ   %00000001   ;EEPROM protection address size

ESTAT:      equ   $115        ;EEPROM status register
;
ECBEIF:     equ   %10000000   ;command buffer empty INT flag
ECCIF:      equ   %01000000   ;command complete interrupt flag
EPVIOL:     equ   %00100000   ;protection violation
EACCERR:    equ   %00010000   ;EEPROM access error
EBLANK:     equ   %00000100   ;array has been verified as erased

ECMD:       equ   $116        ;EEPROM command buffer and register
;
ECMDB6:     equ   %01000000   ;valid flash user mode commands
ECMDB5:     equ   %00100000   ;valid flash user mode commands
ECMDB2:     equ   %00000100   ;valid flash user mode commands
ECMDB0:     equ   %00000001   ;valid flash user mode commands

; $117 reserved for factory test

EADDRHI:    equ   $118        ;flash address high register

EADDRLO:    equ   $119        ;flash address low register

EDATAHI:    equ   $11A        ;flash data high register

EDATALO:    equ   $11B        ;flash data low register



; $11C to $11F reserved for RAM control register



;****  Analog to Digital Converter 10-bit 8 channels (ATD110B8CV2)  *************************
;*
ATD1CTL0:   equ   $120        ;reserved register

ATD1CTL1:   equ   $121        ;reserved register

ATD1CTL2:   equ   $122        ;ATD control register 2

ATD1CTL3:   equ   $123        ;ATD control register 3

ATD1CTL4:   equ   $124        ;ATD control register 4

ATD1CTL5:   equ   $125        ;ATD control register 5

ATD1STAT0:  equ   $126        ;ATD status register 0

; $127 reserved

ATD1TEST0:  equ   $128        ;reserved register (test only)

ATD1TEST1:  equ   $129        ;reserved register (test only)

; $12A reserved

ATD1STAT1:  equ   $12B        ;ATD status register 1

; $12C reserved

ATD1DIEN:   equ   $12D        ;ATD input enable register 1

; $12E reserved

PORTAD1:    equ   $12F        ;port data register 1
;
PTAD17:     equ   %10000000   ;A/D channel 7
PTAD16:     equ   %01000000   ;A/D channel 6
PTAD15:     equ   %00100000   ;A/D channel 5
PTAD14:     equ   %00010000   ;A/D channel 4
PTAD13:     equ   %00001000   ;A/D channel 3
PTAD12:     equ   %00000100   ;A/D channel 2
PTAD11:     equ   %00000010   ;A/D channel 1
PTAD10:     equ   %00000001   ;A/D channel 0

ATD1DR0H:   equ   $130        ;ATD conversion result registers

ATD1DR0L:   equ   $131        ;ATD conversion result registers

ATD1DR1H:   equ   $132        ;ATD conversion result registers

ATD1DR1L:   equ   $133        ;ATD conversion result registers

ATD1DR2H:   equ   $134        ;ATD conversion result registers

ATD1DR2L:   equ   $135        ;ATD conversion result registers

ATD1DR3H:   equ   $136        ;ATD conversion result registers

ATD1DR3L:   equ   $137        ;ATD conversion result registers

ATD1DR4H:   equ   $138        ;ATD conversion result registers

ATD1DR4L:   equ   $139        ;ATD conversion result registers

ATD1DR5H:   equ   $13A        ;ATD conversion result registers

ATD1DR5L:   equ   $13B        ;ATD conversion result registers

ATD1DR6H:   equ   $13C        ;ATD conversion result registers

ATD1DR6L:   equ   $13D        ;ATD conversion result registers

ATD1DR7H:   equ   $13E        ;ATD conversion result registers

ATD1DR7L:   equ   $13F        ;ATD conversion result registers

; ATD1 registers have similar bit definitions as ATD0, see above



;****  Motorola Scalable Can (MSCAN0)  ******************************************************
;*
CAN0CTL0:   equ   $140        ;MSCAN control 0 register
; 
RXFRM:      equ   %10000000   ;receive frame flag
RXACT:      equ   %01000000   ;receive active status
CSWAI:      equ   %00100000   ;CAN stops in wait mode
SYNCH:      equ   %00010000   ;synchronized status
TIME:       equ   %00001000   ;timer enable
WUPE:       equ   %00000100   ;wake-up enable
SLPRQ:      equ   %00000010   ;sleep mode request
INITRQ:     equ   %00000001   ;initialization mode request

CAN0CTL1:   equ   $141        ;MSCAN control 1 register
; 
CANE:       equ   %10000000   ;MSCAN enable
CLKSRC:     equ   %01000000   ;MSCAN clock source
LOOPB:      equ   %00100000   ;loop back self test mode
LISTEN:     equ   %00010000   ;listen only mode
WUPM:       equ   %00000100   ;wake-up mode
SLPAK:      equ   %00000010   ;sleep mode acknowledge
INITAK:     equ   %00000001   ;initialization mode acknowledge

CAN0BTR0:   equ   $142        ;MSCAN timing register 0
; 
SJW1:       equ   %10000000   ;synchronization jump width
SJW0:       equ   %01000000   ;synchronization jump width
BRP5:       equ   %00100000   ;baud rate prescaler
BRP4:       equ   %00010000   ;baud rate prescaler
BRP3:       equ   %00001000   ;baud rate prescaler
BRP2:       equ   %00000100   ;baud rate prescaler
BRP1:       equ   %00000010   ;baud rate prescaler
BRP0:       equ   %00000001   ;baud rate prescaler

CAN0BTR1:   equ   $143        ;MSCAN timing register 1
; 
SAMP:       equ   %10000000   ;sampling
TSEG22:     equ   %01000000   ;time segment 2
TSEG21:     equ   %00100000   ;time segment 2
TSEG20:     equ   %00010000   ;time segment 2
TSEG13:     equ   %00001000   ;time segment 1
TSEG12:     equ   %00000100   ;time segment 1
TSEG11:     equ   %00000010   ;time segment 1
TESG10:     equ   %00000001   ;time segment 1

CAN0RFLG:   equ   $144        ;MSCAN receiver flag register 
; 
WUPIF:      equ   %10000000   ;wake-up interrupt flag
CSCIF:      equ   %01000000   ;CAN status change interrupt flag
RSTAT1:     equ   %00100000   ;receiver status bit
RSTAT0:     equ   %00010000   ;receiver status bit
TSTAT1:     equ   %00001000   ;transmitter status bit
TSTAT0:     equ   %00000100   ;transmitter status bit
OVRIF:      equ   %00000010   ;overrun interrupt flag
RXF:        equ   %00000001   ;receive buffer full 

CAN0RIER:   equ   $145        ;MSCAN receiver INT enable reg
; 
WUPIE:      equ   %10000000   ;wake-up interrupt enable
CSCIE:      equ   %01000000   ;CAN status change interrupt enable
RSTATE1:    equ   %00100000   ;receiver status change enable
RSTATE0:    equ   %00010000   ;receiver status change enable
TSTATE1:    equ   %00001000   ;transmitter status change enable
TSTATE0:    equ   %00000100   ;transmitter status change enable
OVRIE:      equ   %00000010   ;overrun interrupt enable
RXFIE:      equ   %00000001   ;receiver full interrupt enable
	
CAN0TFLG:   equ   $146        ;MSCAN transmitter flag register 
; 
TXE2:       equ   %00000100   ;transmitter buffer empty
TXE1:       equ   %00000010   ;transmitter buffer empty
TXE0:       equ   %00000001   ;transmitter buffer empty

CAN0TIER:   equ   $147        ;MSCAN transmitter INT enable reg
; 
TXEIE2:     equ   %00000100   ;transmitter empty interrupt enable
TXEIE1:     equ   %00000010   ;transmitter empty interrupt enable
TXEIE0:     equ   %00000001   ;transmitter empty interrupt enable

CAN0TARQ:   equ   $148        ;MSCAN transmitter msg abort cntrl 
; 
ABTRQ2:     equ   %00000100   ;abort request
ABTRQ1:     equ   %00000010   ;abort request
ABTRQ0:     equ   %00000001   ;abort request
	
CAN0TAAK:   equ   $149        ;MSCAN transmitter msg abort cntrl
; 
ABTAK2:     equ   %00000100   ;abort acknowledge
ABTAK1:     equ   %00000010   ;abort acknowledge
ABTAK0:     equ   %00000001   ;abort acknowledge

CAN0TBSEL:  equ   $14A        ;MSCAN transmitter buffer selection
; 
TX2:        equ   %00000100   ;transmit buffer select
TX1:        equ   %00000010   ;transmit buffer select
TX0:        equ   %00000001   ;transmit buffer select

CAN0IDAC:   equ   $14B        ;MSCAN id acceptance cntrl reg
; 
IDAM1:      equ   %00100000   ;identifier acceptance mode
IDAM0:      equ   %00010000   ;identifier acceptance mode
IDHIT2:     equ   %00000100   ;id acceptance hit indicator
IDHIT1:     equ   %00000010   ;id acceptance hit indicator
IDHIT0:     equ   %00000001   ;id acceptance hit indicator
	
; $14C AND $14D reserved

CAN0RXERR:  equ   $14E        ;MSCAN receive error counter reg

CAN0TXERR:  equ   $14F        ;MSCAN transmit error counter reg

CAN0IDAR0:  equ   $150        ;MSCAN identifier acceptance reg

CAN0IDAR1:  equ   $151        ;MSCAN identifier acceptance reg

CAN0IDAR2:  equ   $152        ;MSCAN identifier acceptance reg

CAN0IDAR3:  equ   $153        ;MSCAN identifier acceptance reg

CAN0IDMR0:  equ   $154        ;MSCAN identifier mask register

CAN0IDMR1:  equ   $155        ;MSCAN identifier acceptance reg

CAN0IDMR2:  equ   $156        ;MSCAN identifier mask register

CAN0IDMR3:  equ   $157        ;MSCAN identifier mask register

CAN0IDAR4:  equ   $158        ;MSCAN identifier acceptance reg

CAN0IDAR5:  equ   $159        ;MSCAN identifier acceptance reg

CAN0IDAR6:  equ   $15A        ;MSCAN identifier acceptance reg

CAN0IDAR7:  equ   $15B        ;MSCAN identifier acceptance reg

CAN0IDMR4:  equ   $15C        ;MSCAN identifier mask register

CAN0IDMR5:  equ   $15D        ;MSCAN identifier mask register

CAN0IDMR6:  equ   $15E        ;MSCAN identifier mask register

CAN0IDMR7:  equ   $15F        ;MSCAN identifier mask register

; FOREGROUND RECEIVE AND TRANSMIT BUFFER

CAN0RIDR0:  equ   $160

CAN0RIDR1:  equ   $161

CAN0RIDR2:  equ   $162

CAN0RIDR3:  equ   $163

CAN0RDSR0:  equ   $164

CAN0RDSR1:  equ   $165

CAN0RDSR2:  equ   $166

CAN0RDSR3:  equ   $167

CAN0RDSR4:  equ   $168

CAN0RDSR5:  equ   $169

CAN0RDSR6:  equ   $16A

CAN0RDSR7:  equ   $16B

CAN0RDLR:   equ   $16C

; $16D reserved

CAN0RTSRH:  equ   $16E

CAN0RTSRL:  equ   $16F

CAN0TIDR0:  equ   $170

CAN0TIDR1:  equ   $171

CAN0TIDR2:  equ   $172

CAN0TIDR3:  equ   $173

CAN0TDSR0:  equ   $174

CAN0TDSR1:  equ   $175

CAN0TDSR2:  equ   $176

CAN0TDSR3:  equ   $177

CAN0TDSR4:  equ   $178

CAN0TDSR5:  equ   $179

CAN0TDSR6:  equ   $17A

CAN0TDSR7:  equ   $17B

CAN0TDLR:   equ   $17C

CAN0TTBPR:  equ   $17D

CAN0TT