laczipmixer\mc9s12d64equ.inc

freescale的资料

; TIMER CHANNEL 7 REGISTER TC7 IS A 16-BIT REGISTER ($5E:$5F)

T0PACTL:    equ   $60         ;16-bit pulse accumulator cntrl reg
;
PAEN:       equ   %01000000   ;pulse accumulator system enable
PAMOD:      equ   %00100000   ;pulse accumulator mode
PEDGE:      equ   %00010000   ;pulse accumulator edge control
CLK1:       equ   %00001000   ;clock select bit
CLK0:       equ   %00000100   ;clock select bit
PAOVI:      equ   %00000010   ;pulse acc overflow INT enable
PAI:        equ   %00000001   ;pulse accumulator input INT enable

T0PAFLG:    equ   $61         ;pulse accumulator flag register
;
PAOVF:      equ   %00000010   ;pulse accumulator overflow flag
PAIF:       equ   %00000001   ;pulse accumulator input edge flag

T0PACN3:    equ   $62         ;pulse accumulators count registers

T0PACN2:    equ   $63         ;pulse accumulators count registers

T0PACN1:    equ   $64         ;pulse accumulators count registers

T0PACN0:    equ   $65         ;pulse accumulators count registers

T0MCCTL:    equ   $66         ;16-bit modulus down-cntr cntrl reg
;
MCZI:       equ   %10000000   ;modulus cntr underflow INT enable
MODMC:      equ   %01000000   ;modulus mode enable
RDMCL:      equ   %00100000   ;read modulus down-counter load
ICLAT:      equ   %00010000   ;input capture force latch action
FLMC:       equ   %00001000   ;force load reg in modulus cntr reg
MCEN:       equ   %00000100   ;modulus down-counter enable
MCPR1:      equ   %00000010   ;modulus counter prescaler select
MCPR0:      equ   %00000001   ;modulus counter prescaler select

T0MCFLG:    equ   $67         ;16-bit modulus down-cntr FLAG reg
;
MCZF:       equ   %10000000   ;modulus counter underflow flag
POLF3:      equ   %00001000   ;first input cap polarity status
POLF2:      equ   %00000100   ;first input cap polarity status
POLF1:      equ   %00000010   ;first input cap polarity status
POLF0:      equ   %00000001   ;first input cap polarity status

T0ICPAR:    equ   $68         ;input cntrl pulse accumulators reg
;
PA3EN:      equ   %00001000   ;8-bit pulse accumulator 3 enable
PA2EN:      equ   %00000100   ;8-bit pulse accumulator 2 enable
PA1EN:      equ   %00000010   ;8-bit pulse accumulator 1 enable
PA0EN:      equ   %00000001   ;8-bit pulse accumulator 0 enable

T0DLYCT:    equ   $69         ;delay counter control register
;
DLY1:       equ   %00000010   ;delay counter select
DLY0:       equ   %00000001   ;delay counter select

T0ICOVW:    equ   $6A         ;input control overwrite register
;
NOVW7:      equ   %10000000   ;no input capture overwrite
NOVW6:      equ   %01000000   ;no input capture overwrite
NOVW5:      equ   %00100000   ;no input capture overwrite
NOVW4:      equ   %00010000   ;no input capture overwrite
NOVW3:      equ   %00001000   ;no input capture overwrite
NOVW2:      equ   %00000100   ;no input capture overwrite
NOVW1:      equ   %00000010   ;no input capture overwrite
NOVW0:      equ   %00000001   ;no input capture overwrite

T0ICSYS:    equ   $6B         ;input control system control reg
;
SH37:       equ   %10000000   ;share input action of ch 3 and 7
SH26:       equ   %01000000   ;share input action of ch 2 and 6
SH15:       equ   %00100000   ;share input action of ch 1 and 5
SH04:       equ   %00010000   ;share input action of ch 0 and 4
TFMOD:      equ   %00001000   ;timer flag-setting mode
PACMX:      equ   %00000100   ;8-bit pulse accumulators max cnt
BUFEN:      equ   %00000010   ;IC buffer enable
LATQ:       equ   %00000001   ;input ctrl latch/queue mode enable

; $6C reserved

T0TIMTST:   equ   $6D         ;timer test register (test only)
;
TCBYP:      equ   %00000010   ;main timer divider chain bypass

; $6E to $6F reserved

T0PBCTL:    equ   $70         ;16-bit pulse acc B cntrl reg
;
PBEN:       equ   %01000000   ;pulse accumulator B system enable
PBOVI:      equ   %00000010   ;pulse acc B overflow INT enable

T0PBFLG:    equ   $71         ;pulse accumulator B flag register
;
PBOVF:      equ   %00000010   ;pulse accumulator B overflow flag

T0PA3H:     equ   $72         ;8-Bit pulse acc holding reg 3

T0PA2H:     equ   $73         ;8-Bit pulse acc holding reg 2

T0PA1H:     equ   $74         ;8-Bit pulse acc holding reg 1

T0PA0H:     equ   $75         ;8-Bit pulse acc holding reg 0

T0MCCNT:    equ   $76         ;modulus down-counter count reg

; MODULUS COUNTER REGISTER MCCNT IS A 16-BIT REGISTER ($76:$77)

T0TC0H:     equ   $78         ;timer input capture holding reg 0

; TIMER CHANNEL 0 HOLDING REGISTER TC0H IS A 16-BIT REGISTER ($78:$79)

T0TC1H:     equ   $7A         ;timer input capture holding reg 1

; TIMER CHANNEL 1 HOLDING REGISTER TC1H IS A 16-BIT REGISTER ($7A:$7B)

T0TC2H:     equ   $7C         ;timer input capture holding reg 2

; TIMER CHANNEL 2 HOLDING REGISTER TC2H IS A 16-BIT REGISTER ($7C:$7D)

T0TC3H:     equ   $7E         ;timer input capture holding reg 3

; TIMER CHANNEL 3 HOLDING REGISTER TC3H IS A 16-BIT REGISTER ($7E:$7F)



;****  Analog to Digital Converter 10-bit 8 channels (ATD010B8CV2)  *************************
;*
ATD0CTL0:   equ   $80         ;reserved register

ATD0CTL1:   equ   $81         ;reserved register

ATD0CTL2:   equ   $82         ;ATD control register 2
;
ADPU:       equ   %10000000   ;ATD power down
AFFC:       equ   %01000000   ;ATD fast flag clear all
AWAI:       equ   %00100000   ;ATD power down in wait mode
ETRIGLE:    equ   %00010000   ;external trigger level/edge cntrl
ETRIGP:     equ   %00001000   ;external trigger polarity
ETRIGE:     equ   %00000100   ;external trigger mode enable
ASCIE:      equ   %00000010   ;ATD sequence complete INT enable
ASCIF:      equ   %00000001   ;ATD sequence complete INT flag

ATD0CTL3:   equ   $83         ;ATD control register 3
;
S8C:        equ   %01000000   ;conversion sequence length
S4C:        equ   %00100000   ;conversion sequence length
S2C:        equ   %00010000   ;conversion sequence length
S1C:        equ   %00001000   ;conversion sequence length
FIFO:       equ   %00000100   ;result register FIFO mode
FRZ1:       equ   %00000010   ;background debug freeze enable
FRZ0:       equ   %00000001   ;background debug freeze enable

ATD0CTL4:   equ   $84         ;ATD control register 4
;
SRES8:      equ   %10000000   ;A/D resolution select
SMP1:       equ   %01000000   ;sample time select
SMP0:       equ   %00100000   ;sample time select
PRS4:       equ   %00010000   ;ATD clock prescaler
PRS3:       equ   %00001000   ;ATD clock prescaler
PRS2:       equ   %00000100   ;ATD clock prescaler
PRS1:       equ   %00000010   ;ATD clock prescaler
PRS0:       equ   %00000001   ;ATD clock prescaler

ATD0CTL5:   equ   $85         ;ATD control register 5
;
DJM:        equ   %10000000   ;result register data justification
DSGN:       equ   %01000000   ;result data signed/unsigned rep
SCAN:       equ   %00100000   ;cont conversion sequence mode
MULT:       equ   %00010000   ;multi-channel sample mode
CC:         equ   %00000100   ;analog input channel select code
CB:         equ   %00000010   ;analog input channel select code
CA:         equ   %00000001   ;analog input channel select code

ATD0STAT0:  equ   $86         ;ATD status register 0
;
SCF:        equ   %10000000   ;sequence complete flag
ETORF:      equ   %00100000   ;external trigger overrun flag
FIFOR:      equ   %00010000   ;FIFO over run flag
CC2:        equ   %00000100   ;conversion counter
CC1:        equ   %00000010   ;conversion counter
CC0:        equ   %00000001   ;conversion counter

; $87 reserved

ATD0TEST0:  equ   $88         ;reserved register (test only)

ATD0TEST1:  equ   $89         ;reserved register (test only)
;
SC:         equ   %00000001   ;special channel conversion bit

; $8A reserved

ATD0STAT1:  equ   $8B         ;ATD status register 1
;
CCF7:       equ   %10000000   ;conversion complete flag 7
CCF6:       equ   %01000000   ;conversion complete flag 6
CCF5:       equ   %00100000   ;conversion complete flag 5
CCF4:       equ   %00010000   ;conversion complete flag 4
CCF3:       equ   %00001000   ;conversion complete flag 3
CCF2:       equ   %00000100   ;conversion complete flag 2
CCF1:       equ   %00000010   ;conversion complete flag 1
CCF0:       equ   %00000001   ;conversion complete flag 0

; $8C reserved

ATD0DIEN:   equ   $8D         ;ATD input enable register 1
;
IEN7:       equ   %10000000   ;ATD digital input enable on ch 7
IEN6:       equ   %01000000   ;ATD digital input enable on ch 6
IEN5:       equ   %00100000   ;ATD digital input enable on ch 5
IEN4:       equ   %00010000   ;ATD digital input enable on ch 4
IEN3:       equ   %00001000   ;ATD digital input enable on ch 3
IEN2:       equ   %00000100   ;ATD digital input enable on ch 2
IEN1:       equ   %00000010   ;ATD digital input enable on ch 1
IEN0:       equ   %00000001   ;ATD digital input enable on ch 0

; $8E reserved

PORTAD0:    equ   $8F         ;port data register 1
;
PTAD7:      equ   %10000000   ;A/D channel 7
PTAD6:      equ   %01000000   ;A/D channel 6
PTAD5:      equ   %00100000   ;A/D channel 5
PTAD4:      equ   %00010000   ;A/D channel 4
PTAD3:      equ   %00001000   ;A/D channel 3
PTAD2:      equ   %00000100   ;A/D channel 2
PTAD1:      equ   %00000010   ;A/D channel 1
PTAD0:      equ   %00000001   ;A/D channel 0

ATD0DR0H:   equ   $90         ;ATD conversion result registers

ATD0DR0L:   equ   $91         ;ATD conversion result registers

ATD0DR1H:   equ   $92         ;ATD conversion result registers

ATD0DR1L:   equ   $93         ;ATD conversion result registers

ATD0DR2H:   equ   $94         ;ATD conversion result registers

ATD0DR2L:   equ   $95         ;ATD conversion result registers

ATD0DR3H:   equ   $96         ;ATD conversion result registers

ATD0DR3L:   equ   $97         ;ATD conversion result registers

ATD0DR4H:   equ   $98         ;ATD conversion result registers

ATD0DR4L:   equ   $99         ;ATD conversion result registers

ATD0DR5H:   equ   $9A         ;ATD conversion result registers

ATD0DR5L:   equ   $9B         ;ATD conversion result registers

ATD0DR6H:   equ   $9C         ;ATD conversion result registers

ATD0DR6L:   equ   $9D         ;ATD conversion result registers

ATD0DR7H:   equ   $9E         ;ATD conversion result registers

ATD0DR7L:   equ   $9F         ;ATD conversion result registers



;****  Pulse Width Modulator (PWM8B8CV1)  ***************************************************
;*  
PWME:       equ   $A0         ;PWM enable register
;
PWME7:      equ   %10000000   ;pulse width channel 7 enable
PWME6:      equ   %01000000   ;pulse width channel 6 enable
PWME5:      equ   %00100000   ;pulse width channel 5 enable
PWME4:      equ   %00010000   ;pulse width channel 4 enable
PWME3:      equ   %00001000   ;pulse width channel 3 enable
PWME2:      equ   %00000100   ;pulse width channel 2 enable
PWME1:      equ   %00000010   ;pulse width channel 1 enable
PWME0:      equ   %00000001   ;pulse width channel 0 enable

PWMPOL:     equ   $A1         ;PWM polarity register
;
PPOL7:      equ   %10000000   ;pulse width channel 7 polarity
PPOL6:      equ   %01000000   ;pulse width channel 6 polarity
PPOL5:      equ   %00100000   ;pulse width channel 5 polarity
PPOL4:      equ   %00010000   ;pulse width channel 4 polarity
PPOL3:      equ   %00001000   ;pulse width channel 3 polarity
PPOL2:      equ   %00000100   ;pulse width channel 2 polarity
PPOL1:      equ   %00000010   ;pulse width channel 1 polarity
PPOL0:      equ   %00000001   ;pulse width channel 0 polarity

PWMCLK:     equ   $A2         ;PWM clock select register
;
PCLK7:      equ   %10000000   ;pulse width channel 7 clock select
PCLK6:      equ   %01000000   ;pulse width channel 6 clock select
PCLK5:      equ   %00100000   ;pulse width channel 5 clock select
PCLK4:      equ   %00010000   ;pulse width channel 4 clock select
PCLK3:      equ   %00001000   ;pulse width channel 3 clock select
PCLK2:      equ   %00000100   ;pulse width channel 2 clock select
PCLK1:      equ   %00000010   ;pulse width channel 1 clock select
PCLK0:      equ   %00000001   ;pulse width channel 0 clock select

PWMPRCLK:   equ   $A3         ;PWM prescale clock select register
;
PCKB2:      equ   %01000000   ;prescaler select for clock B
PCKB1:      equ   %00100000   ;prescaler select for clock B
PCKB0:      equ   %00010000   ;prescaler select for clock B
PCKA2:      equ   %00000100   ;prescaler select for clock A
PCKA1:      equ   %00000010   ;prescaler select for clock A
PCKA0:      equ   %00000001   ;prescaler select for clock A

PWMCAE:     equ   $A4         ;PWM center align enable register
;
CAE7:       equ   %10000000   ;center aligned output mode on channel 7
CAE6:       equ   %01000000   ;center aligned output mode on channel 6
CAE5:       equ   %00100000   ;center aligned output mode on ch 5
CAE4:       equ   %00010000   ;center aligned output mode on ch 4
CAE3:       equ   %00001000   ;center aligned output mode on ch 3
CAE2:       equ   %00000100   ;center aligned output mode on ch 2
CAE1:       equ   %00000010   ;center aligned output mode on ch 1
CAE0:       equ   %00000001   ;center aligned output mode on ch 0

PWMCTL:     equ   $A5         ;PWM control register
;
CON67:      equ   %10000000   ;concatenate channels 6 and 7
CON45:      equ   %01000000   ;concatenate channels 4 and 5
CON23:      equ   %00100000   ;concatenate channels 2 and 3
CON01:      equ   %00010000   ;concatenate channels 0 and 1
PSWAI:      equ   %00001000   ;PWM stops in wait mode
PFRZ:       equ   %00000100   ;PWM counters stop in freeze mode

PWMTST:     equ   $A6         ;reserved

PWMPRSC:    equ   $A7         ;reserved

PWMSCLA:    equ   $A8         ;PWM scale A register

PWMSCLB:    equ   $A9         ;PWM scale B register

PWMSCNTA:   equ   $AA         ;reserved (test only)

PWMSCNTB:   equ   $AB         ;reserved (test only)

PWMCNT0:    equ   $AC         ;PWM channel counter register

PWMCNT1:    equ   $AD         ;PWM channel counter register

PWMCNT2:    equ   $AE         ;PWM channel counter register